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intersil|techwell 1 rev a 10/25 /2010 TW8833/TW8833s -- tft display controller datasheet from intersil|techwell . information may change without notice disclaimer this document provides technical information for the user. intersil corporation reserves the right to modify the information in this document as necessary. the customer should make sure that they have the most recent data sheet version . intersil corporation holds no responsibility for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. intersil corporation respects valid patent righ ts of third parties and does not infringe upon or assist others to infringe upon such rights. t e c h w e l l
TW8833/TW8833s C tft display controll er intersil|techwell 2 rev a 10/25 /2010 introduction ................................ ................................ ....................... 6 applications ................................ ................................ ............................. 6 tft panel support ................................ ................................ ............... 6 on screen display ................................ ................................ ............... 6 image processing ................................ ................................ ................ 6 clock generation ................................ ................................ .................. 6 power management ................................ ................................ ............ 6 miscellaneous ................................ ................................ ....................... 6 order information ................................ ................................ ............. 8 functional description ................................ ................................ .... 9 overview ................................ ................................ ................................ ... 9 analog front - end ................................ ................................ .................... 9 video decoder ................................ ................................ ......................... 9 sync processor ................................ ................................ ..................... 9 color decoding ................................ ................................ ................... 10 automatic standard detection ................................ ............................ 10 video format support ................................ ................................ ........ 10 input image control ................................ ................................ .............. 12 image scaling ................................ ................................ ........................ 12 image enhancement processing ................................ ...................... 12 black/white stretch ................................ ................................ ............ 12 tft panel support ................................ ................................ ................ 12 dithering ................................ ................................ .............................. 12 gamma table ................................ ................................ .................... 12 tcon ................................ ................................ ................................ .. 12 font on screen display ................................ ................................ ....... 13 on chip osd functions ................................ ................................ ...... 13 basic register setting flow example for built - in osd controller ....... 14 osd window start location: built - in osd controller ...................... 17 osd_ram configuration ................................ ................................ .. 17 alpha blending for osd window ................................ ..................... 18 alpha blending concept ................................ ................................ .... 18 spi on screen display (for TW8833s onl y) ................................ .... 19 spiosd window display starting location and sizes .................. 19 spiosd window buffer memory ................................ ..................... 20 spiosd window loop control ................................ ........................ 21 osd display path ................................ ................................ .............. 22 microcontroller interface ................................ ................................ ..... 23 two wire serial bus interface ................................ ........................... 23 pin diagram ................................ ................................ ..................... 26 pin description ................................ ................................ ............... 27 parametric information ................................ ................................ .. 30 ac/dc electrical parameters ................................ .............................. 30 filter curves ................................ ................................ .................... 33 anti - alias filter ................................ ................................ ...................... 33 decimation filter ................................ ................................ .................. 33 chroma band pass filter curves ................................ ..................... 34 luma notch filter curve for ntsc and pal ................................ .. 34 chrominance low - pass filter curve ................................ ............... 35 mechanical data 48 qfn ................................ ............................. 36 register summary ................................ ................................ ......... 38 general ................................ ................................ ................................ 38 general ................................ ................................ ................................ 38 ledc/dc - dc/vcom control ................................ .......................... 39 dac ................................ ................................ ................................ ..... 39 sspll ................................ ................................ ................................ . 39 decoder ................................ ................................ ............................... 40 scaler / tcon ................................ ................................ ............... 42 image adjustment ................................ ................................ .............. 43 gamma & dither ................................ ................................ ................ 43 fosd ................................ ................................ ................................ .. 44 spi osd (for TW8833s only) ................................ ........................... 46 spi interface ................................ ................................ ....................... 48 register description ................................ ................................ ...... 49 0x000 C product id code register (id) ................................ ........... 49 0x002 C irq ................................ ................................ ........................ 49 0x003 C imask ................................ ................................ .................. 49 0x006 C srst ................................ ................................ .................... 49 0x007 C output ctrl i ................................ ................................ . 50 0x008 C output ctrl ii ................................ ................................ 50 0x009 C gpo control ................................ ................................ ........ 51 0x01f C test ................................ ................................ .................... 51 0x0db C fpwm_hi ................................ ................................ ........... 52 0x0dc C fpwm1_lo ................................ ................................ ....... 52 0x0dd C dpwm1 ................................ ................................ .............. 52 0x0de C fpwm2_lo ................................ ................................ ....... 52 0x0df C dpwm2 ................................ ................................ ............... 52 0x0e0 C ledc control i ................................ ................................ .... 53 0x0e1 C ledc sense control ................................ .......................... 53 0x0e2 C ledc control ii ................................ ................................ ... 53 0x0e3 C ledc pwm ................................ ................................ ........ 54 0x0e4 C ledc dim frequency ................................ ........................ 54 0x0e5 C ledc dim cont rol ................................ .............................. 54 0x0e6 C ledc pwmtop ................................ ................................ 54 0x0e8 C dcdc control i ................................ ................................ ... 55 0x0e9 C dcdc sense control ................................ ......................... 55 0x0ea C dcdc control ii ................................ ................................ .. 55 0x0eb C dcdc pwm ................................ ................................ ....... 56 0x0ec C dcdc pwmtop ................................ .............................. 56 0x0ed C vcom - dc offset control ................................ ............ 56 0x0ee C vcom - ac amp control ................................ .................... 56 0x0f0 C dac i ................................ ................................ .................... 57 0x0f1 C dac ii ................................ ................................ ................... 57 0x0f6 C clock_div ................................ ................................ ........ 57 0x0f7 C sspll ................................ ................................ .................. 57 0x0f8 C sspll control registers ................................ ................... 57 0x0f9 C sspll frequency control registers ................................ 58 0x0fa C sspll frequency control registers ................................ 58 0x0fb C sspll modulation frequency control registers ............ 58 0x0fc C sspll ................................ ................................ ................. 58 0x0fd C sspll analog control registers ................................ ...... 59 0x0fe C fpga debug ................................ ................................ ...... 59 decoder ................................ ................................ ............................... 60 0x101 C chip status register (cstatus) ................................ ..... 60 0x102 C input format (inform) ................................ ...................... 60 0x103 C reserved ................................ ................................ .............. 61 0x104 C hsync delay control ................................ ........................ 61 0x105 C ant i - aliasing ................................ ................................ .......... 61 0x106 C analog control register (acntl) ................................ ..... 62 0x107 C cropping register, high (crop_hi) ................................ 62 0x108 C vertical delay register, low (vdelay_lo) .................... 62 0x109 C vertical active register, low (vactive_lo) .................. 63 0x10a C horizontal delay register, low (hdelay_lo) .............. 63 0x10b C horizontal active register, low (hactive_lo) ............. 63 0x 10c C control register i (cntrl1) ................................ ............. 64 0x10d C cc/wss control ................................ ................................ . 64 0x110 C brightness control register (bright) ..................... 64 0x111 C contrast control register (contrast) .................. 65 0x112 C sharpness control register i (sharpness) ........... 65 0x113 C chroma (u) gain register (sat_u) ................................ . 65 0x114 C chroma (v) gain register (sat_v) ................................ .. 65 0x115 C hue control r egister (hue) ................................ ............... 66 0x116 C reserved ................................ ................................ .............. 66 0x117 C vertical peaking control i ................................ .................... 66 0x118 C coring control register (coring) ................................ ... 66 0x119 C reserved ................................ ................................ .............. 66 0x11a C cc/eds status register (cc_status) ......................... 67 0x11b C cc/eds data register (cc_data) ................................ 67 0x11c C standard selection (sdt) ................................ .................. 67 0x11d C standard recognition (sdtr) ................................ .......... 68 0x11e C component video format (cvfmt) ................................ 68 0x11f C test ................................ ................................ ....................... 68 0x120 C clamping gain (clmpg) ................................ ................... 69 0x121 C individual agc gain (iagc) ................................ ............... 69 0x122 C agc gain (agcgain) ................................ ....................... 69 0x123 C white peak threshold (peakwt) ................................ .... 69 0x124 C clamp level (clmpl) ................................ ........................... 69 0x125 C sync amplitude (synct) ................................ .................... 70 0x126 C sync miss count register (misscnt) ............................. 70 0x127 C clamp position regist er (pclamp) ................................ . 70
TW8833/TW8833s C tft display controll er intersil|techwell 3 rev a 10/25 /2010 0x128 C vertical control i ................................ ................................ ... 70 0x129 C vertical control ii ................................ ................................ .. 71 0x12a C color killer level control ................................ .................... 71 0x12b C comb filter control ................................ ............................. 71 0x12c C luma delay and hfilter control ................................ ........ 71 0x12d C miscellaneous control register i (misc1) ....................... 72 0x12e C miscellaneous control register ii (misc2) ....................... 72 0x12f C miscellaneous control iii (misc3) ................................ ..... 73 0x130 C macrovision detection ................................ ......................... 73 0x131 C chip s tatus ii (cstatus2) ................................ ........... 74 0x132 C h monitor (hfref) ................................ ............................. 74 0x133 C clamp mode(clmd) ................................ ...................... 74 0x134 C id detection control (nsen/ssen/psen/wkth) ......... 75 0x135 C clamp control (clcntl) ................................ ................... 75 0x140 C wss0 ................................ ................................ ................... 75 0x141 C wss1 ................................ ................................ ................... 75 0x142 C wss2 ................................ ................................ ................... 75 scaler ................................ ................................ ............................. 76 0x201 C general scaler control ................................ ........................ 76 0x202 C scaling offset control ................................ ........................... 76 0x203 C xscale_lo ................................ ................................ ........ 76 0x204 C xscale_hi ................................ ................................ .......... 76 0x205 C yscale_lo ................................ ................................ ........ 77 0x206 C yscale_hi ................................ ................................ .......... 77 0x207 C pxscale ................................ ................................ ............. 77 0x208 C pxinc ................................ ................................ ................... 77 0x209 C hdscale_lo ................................ ................................ ..... 77 0x20a C hdscale_hi ................................ ................................ ...... 77 0x20b C hdelay2 ................................ ................................ ............. 78 0x20c C hactive2_lo ................................ ................................ .... 78 0x20d C hactive2_hi ................................ ................................ ..... 78 0x20e C hpadj_hi ................................ ................................ ............ 78 0x20f C hpadj_lo ................................ ................................ ........... 78 0x210 C ha_pos ................................ ................................ ............... 78 0x211 C ha_len_lo ................................ ................................ ........ 79 0x212 C ha_len_hi ................................ ................................ .......... 79 0x213 C hs_pos ................................ ................................ ............... 79 0x214 C hs_len ................................ ................................ ................ 79 0x215 C va_pos ................................ ................................ ................ 79 0x216 C va_len_lo ................................ ................................ ......... 79 0x217 C va_len_hi ................................ ................................ .......... 79 0x218 C vs_len_pos ................................ ................................ ...... 80 0x219 C lntt_lo ................................ ................................ .............. 80 0x21a C dm_top ................................ ................................ .............. 80 0x21b C dm_bot ................................ ................................ .............. 80 tcon ................................ ................................ ................................ .. 81 0x240 C csp control ................................ ................................ .......... 81 0x241 C clp position ................................ ................................ ......... 81 0x242 C cl p width ................................ ................................ ............. 81 0x243 C rck control hi ................................ ................................ ..... 81 0x244 C rck position lo ................................ ................................ .. 81 0x 245 C rck width lo ................................ ................................ ...... 81 0x246 C roe control hi ................................ ................................ ..... 82 0x247 C roe position lo ................................ ................................ .. 82 0x248 C roe width lo ................................ ................................ ...... 82 0x249 C rsp control ................................ ................................ .......... 82 0x24a C rsp position control ................................ ............................ 82 0x24b C cpl position control ................................ ............................ 83 0x24c C cpl position control lo ................................ ...................... 83 0x24d C tcon control i ................................ ................................ .... 83 0x24e C tcon control ii ................................ ................................ ... 84 0x 28 0 C image adjustment register ................................ ................ 85 0x 281 C image adjus tment register ................................ ................ 85 0x 282 C image adjustment register ................................ ................ 85 0x 283 C image adjustment register ................................ ................ 85 0x 284 C image adjustment register ................................ ................ 85 0x 285 C image adjustment register ................................ ................ 85 0x 286 C image adjustment r egister ................................ ................ 86 0x 287 C image adjustment register ................................ ................ 86 0x 288 C image adjustment register ................................ ................ 86 0x 289 C image adjustment register ................................ ................ 86 0x 28a C image adjustment register ................................ ................ 86 0x 28b C image adjustment register ................................ ................ 86 0x 28c C image adjustment register ................................ ............... 87 0x 2b0 C image adjustment register ................................ ................ 87 0x 2b1 C image adjustment register ................................ ................ 87 0x 2b2 C image adjustment register ................................ ................ 87 0x 2b6 C image adjustment register ................................ ................ 87 0x 2b7 C image adjustment register ................................ ................ 87 0x 2bf C test pattern generator register ................................ ....... 88 0x 2e0 C gamma control register ................................ ................... 89 0x 2e1 C gamma table address port register ............................... 89 0x 2e2 C gamma table data port regist er ................................ ..... 89 0x 2e3 C gamma table data port register ................................ ..... 89 0x 2e4 C dither option register ................................ ........................ 90 0x 2f0 C rgb level readout register ................................ ............ 91 0x 2f1 C rgb level readout register ................................ ............ 91 0x 2f2 C rgb level readout register ................................ ............ 91 0x 2f3 C rgb level readout register ................................ ............ 91 0x 2f4 C rgb level readout register ................................ ............ 91 0x 2f5 C rgb level readout register ................................ ............ 91 0x 2f8 C 8 - bit panel interface register ................................ ............. 92 0x 2f9 C 8 - bit panel interface re gister ................................ ............. 92 0x300 C font osd control register ................................ ................. 93 0x301 C test register ................................ ................................ ........ 93 0x302 C test register ................................ ................................ ........ 93 0x303 C font osd control register ................................ ................. 93 0x304 C font osd control register ................................ ................. 93 0x305 C font osd control register ................................ ................. 94 0x306 C osd ram address register ................................ ............. 94 0x307 C osd ram data port hi register ................................ ....... 94 0x308 C osd ram data port lo register ................................ ...... 94 0x309 C font ram address register ................................ .............. 94 0x30a C font ram data port ................................ ........................... 94 0x30b C multi - color font start position register ............................ 94 0x3 0c C font osd control register ................................ ................ 95 0x30d C character color look - up table data port high byte register ................................ ................................ ............................... 95 0x30e C character color look - up table data port low byte register ................................ ................................ ............................... 95 0x310 C osd window1 control register ................................ ........ 95 0x311 C osd window1 control register ................................ ........ 95 0x312 C osd window1 control register ................................ ........ 96 0x313 C osd window1 control register ................................ ........ 96 0x314 C osd window1 control register ................................ ........ 96 0x315 C osd window1 control register ................................ ........ 96 0x316 C osd window1 control regis ter ................................ ....... 96 0x317 C osd window1 control register ................................ ........ 96 0x318 C osd window1 control register ................................ ........ 97 0x319 C osd window1 control register ................................ ........ 97 0x31a C osd window1 control register ................................ ....... 97 0x31b C osd window1 contr ol register ................................ ....... 97 0x31c C osd window1 control register ................................ ....... 97 0x31d C osd window1 control register ................................ ...... 98 0x31e C osd window1 control register ................................ ....... 98 0x31f C osd window1 control register ................................ ........ 98 0x320 C osd wind ow2 control register ................................ ........ 98 0x321 C osd window2 control register ................................ ........ 98 0x322 C osd window2 control register ................................ ........ 99 0x323 C osd window2 control register ................................ ........ 99 0x324 C osd window2 control register ................................ ........ 99 0x325 C osd window2 control register ................................ ........ 99 0x326 C osd window2 control register ................................ ........ 99 0x327 C osd window2 control register ................................ ........ 99 0x328 C osd window2 control register ................................ ...... 100 0x329 C osd window2 control register ................................ ...... 100 0x32a C osd window2 control register ................................ ..... 100 0x32b C osd window2 control register ................................ ..... 100 0x32c C osd window2 control register ................................ ..... 100 0x32d C osd window2 control register ................................ ..... 101
TW8833/TW8833s C tft display controll er intersil|techwell 4 rev a 10/25 /2010 0x32e C osd window2 control register ................................ ..... 101 0x32f C osd window2 control register ................................ ...... 101 0x330 C osd window3 control register ................................ ...... 101 0x331 C osd window3 control reg ister ................................ ...... 101 0x332 C osd window3 control register ................................ ...... 102 0x333 C osd window3 control register ................................ ...... 102 0x334 C osd window3 control register ................................ ...... 102 0x335 C osd window3 control register ................................ ...... 102 0x336 C osd window 3 control register ................................ ...... 102 0x337 C osd window3 control register ................................ ...... 102 0x338 C osd window3 control register ................................ ...... 103 0x339 C osd window3 control register ................................ ...... 103 0x33a C osd window3 control register ................................ ..... 103 0x33b C osd window3 control register ................................ ..... 103 0x33c C osd window3 control register ................................ ..... 103 0x33d C osd window3 control register ................................ ..... 104 0x33e C osd window3 control register ................................ ..... 104 0x33f C osd window3 control register ................................ ...... 104 0x340 C osd window4 control register ................................ ...... 104 0x341 C osd window4 control register ................................ ...... 104 0x342 C osd window4 control register ................................ ...... 105 0x343 C osd window4 control register ................................ ...... 105 0x344 C osd window4 control register ................................ ...... 105 0x345 C osd window4 control register ................................ ...... 105 0x346 C osd window4 control register ................................ ...... 105 0x347 C osd window4 contr ol register ................................ ...... 105 0x348 C osd window4 control register ................................ ...... 106 0x349 C osd window4 control register ................................ ...... 106 0x34a C osd window4 control register ................................ ..... 106 0x34b C osd window4 control register ................................ ..... 106 0x34c C osd window4 control register ................................ ..... 106 0x34d C osd window4 control register ................................ ..... 107 0x34e C osd window4 control register ................................ ..... 10 7 0x34f C osd window4 control register ................................ ...... 107 spi osd 0x400~ 0x457 (for TW8833s only) ............................... 108 0x400 C osd control register ................................ ....................... 108 0x40f C spiosd timing adjustment register ............................. 108 0x410 C 8 - bit spiosd look up table access con trol register 108 0x411 C 8 bit spiosd look up table address [7:0] register .... 108 0x412 C 8 bit spiosd look up table data port [7: 0] register .. 109 0x420 C spiosd window 0 enable register ............................... 109 0x421 ~ 0x422 C spiosd window 0 horizontal start [10:0] registers ................................ ................................ ........................... 109 0x421 C high byte register ................................ ............................. 109 0x422 C low byte register ................................ ............................. 109 0 x423~0x424 C spiosd window 0 vertical start [10:0] registers ................................ ................................ ........................... 110 0x423 C high byte register ................................ ............................. 110 0x424 C low byte register ................................ ............................. 110 0x425~0x0426 C spiosd window 0 horizontal length [11:0] registers ................................ ................................ ........................... 110 0x0425 C high byte register ................................ .......................... 110 0x426 C low byte register ................................ ............................. 110 0x427~0x0428 C spiosd window 0 vertical length [11:0] registers ................................ ................................ ........................... 110 0x427 C high byte register ................................ ............................. 110 0x428 C low byte register ................................ ............................. 110 0x429 C 0x42b spiosd window 0 buffer memory starting address [23:0] register ................................ ................................ ... 111 0x429 C high byte register ................................ ............................. 111 0x42a C mid byte register ................................ .............................. 111 0x42b C low byte register ................................ ............................. 111 0x42c~0x42d C spiosd window 0 buffer horizontal length [11:0] registers ................................ ................................ ................. 111 0x42c C high byte register ................................ ............................ 111 0x42d C low byte register ................................ ............................. 111 0x42e~0x42f C spiosd window 0 buffer vertical length [11:0] registers ................................ ................................ ........................... 111 0x42e C high byte register ................................ ............................ 111 0x42f C low byte register ................................ ............................. 111 0 x430~0x431 C spiosd window 0 image horizontal start [10:0] registers ................................ ................................ ........................... 112 0x430 C high byte register ................................ ............................. 112 0x431 C low byte registe r ................................ .............................. 112 0x432~0x434 CC spiosd window 0 image vertical start [10:0] registers ................................ ................................ ........................... 112 0x432 C high byte register ................................ ............................. 112 0x433 C low byte register ................................ ............................. 112 0x434 C spiosd window 0 global alpha value [6:0] register .. 112 0x435~0x437 C spiosd window 0 loop control registers ...... 113 0x435 C looping horizontal frame number register .................. 113 0x436 C looping vertical frame number register ...................... 113 0x437 C frame duration register ................................ .................. 113 0x440 C spiosd window 1 enable register ............................... 113 0x441~ 0x442 C spiosd window 1 horizontal start [10:0] registers ................................ ................................ ........................... 114 0x441 C high byte register ................................ ............................. 114 0x442 C low byte register ................................ ............................. 114 0x443~0x444 C spiosd window 1 vertical start [10:0] registers ................................ ................................ ........................... 114 0 x443 C high byte register ................................ ............................. 114 0x444 C low byte register ................................ ............................. 114 0x445~0x446 C spiosd window 1 horizontal length [11:0] registers ................................ ................................ ........................... 114 0x445 C high byte register ................................ ............................. 114 0x446 C low byte register ................................ ............................. 114 0x 447~0x448 C spiosd window 1 vertical length [11:0] registers ................................ ................................ ........................... 115 0x447 C high byte register ................................ ............................. 115 0x448 C low byte register ................................ ............................. 115 0x449~0x044b C spiosd window 1 buffer memory starting address [23:0] registers ................................ ................................ .. 115 0x0449 C high byte register ................................ .......................... 115 0x44a C mid byte register ................................ .............................. 115 0x44b C low byte register ................................ ............................. 115 0x44c~0x044d C spi osd window 1 buffer horizontal length [11:0] registers ................................ ................................ ................. 115 0x44c C high byte register ................................ ............................ 115 0x44d C low byte register ................................ ............................. 115 0x44e~0x44f C spiosd window 1 buffer vertical length [11:0] registers ................................ ................................ ........................... 116 0x44e C high byte register ................................ ............................ 116 0x44f C low byte register ................................ ............................. 116 0x450~0x51f C spiosd window 1 image horizontal start [10:0] registers ................................ ................................ ........................... 116 0x450 C high byte register ................................ ............................. 116 0x451 C low byte register ................................ ............................. 116 0x452~0x453 C spiosd window 1 image vertical start [10:0] registers ................................ ................................ ........................... 116 0x452 C high byte register ................................ ............................. 116 0x453 C low byte register ................................ ............................. 116 0x454 C spiosd window 1 global alpha value [6:0] register .. 116 0x455~0x457 C spiosd window 1 loop control registers ...... 117 0x455 C looping horizontal frame number register .................. 117 0x456 C looping vertical frame number register ...................... 117 0x457 C frame duration register ................................ .................. 117 spi interface ................................ ................................ ..................... 118 0x480 C spi flash mode control register ................................ .... 118 0x481 C spi flash mode control register ................................ .... 118 0x483 C dma control register ................................ ....................... 118 0x484 C flash busy control register ................................ ............. 119 0x485 C wait control register ................................ ........................ 119 0x486 C dma page register ................................ .......................... 119 0x487 C dma index register ................................ .......................... 119 0x488 C dma length mid byte register ................................ ....... 119 0x489 C dma length low byte register ................................ ...... 119 0x48a C dma command buffer register ................................ ..... 120 0x48b C dma command buffer2 register ................................ ... 120 0x48c C dma command buffer3 register ................................ ... 120 0x48d C dma command buffer4 register ................................ ... 120
TW8833/TW8833s C tft display controll er intersil|techwell 5 rev a 10/25 /2010 0x48e C dma command buffer5 register ................................ ... 120 0x490 C dma read/write buffer1 register ................................ ... 120 0x491 C dma read/write buffer2 register ................................ ... 120 0x492 C dma read/write buffer3 register ................................ ... 121 0x493 C dma read/write buffer4 register ................................ ... 121 0x494 C dma read/w rite buffer5 register ................................ ... 121 0x495 C dma read/write buffer6 register ................................ ... 121 0x496 C dma read/write buffer7 register ................................ .. 121 0x497 C dma read/write buffer8 register ................................ ... 121 0x498 C spi flash status command register ............................. 121 0x499 C spi flash busy control register ................................ ...... 122 0x49a C dma length high byte register ................................ ..... 122 copyright notice ................................ ................................ .......... 123 trademark acknowledgment ................................ .................... 123 disclaimer ................................ ................................ ..................... 123 life support policy ................................ ................................ ...... 123 revision history ................................ ................................ ................ 123
TW8833/TW8833s C tft display controll er intersil|techwell 6 rev a 10/25 /2010 introduction applications - in - car display controller - portable dvd and dvrs players - portable media player description the TW8833 incorporates many of the features required to create multi - purpose in - car lcd display system in a single package. it integrates a high quality 2d comb ntsc/pal/secam video decoder, triple high speed rgb adcs, high quality scaler , triple dacs and images enhancement func tions which include black and white stretch and etc. it also supports panoramic scaling for conversion to wide screen display. on the input side, it supports a rich combination of cvbs, s - video and analog component inputs. on the output side, it supports a nalog panel type with its built - in timing controller. ? analog video decoder ? ntsc (m, 4.34) and pal (b, d, g, h, i, m, n, n combination), pal (60), secam with automatic format detection ? three 10 - bit adcs and analog clamping circuit ? fully programmable sta tic gain or automatic gain control for the y or cvbs channel ? programmable white peak control for the y or cvbs channel ? software selectable analog inputs ? high quality adaptive 2d comb filter for both ntsc and pal standards ? pal delay line for color phase err or correction ? image enhancement with 2d dynamic peaking and cti ? digital sub - carrier pll for accurate color decoding ? digital horizontal pll and advanced synchronization processing for vcr playback and weak signal performance ? programmable hue, brightness, s aturation, contrast and sharpness ? high quality horizontal and vertical filtered down scaling with arbitrary scale down ratio ? detection of level of copy protection according to macrovision standard tft panel support ? built - in programmable timing controller ? s upports 3, 4, 6 or 8 bits per pixel up to 16.8 million colors with built - in dithering engine ? support analog panel up to wqvga resolution ? support serial (8bit) rgb panel on screen display ? integrated 256 programmable font ram and 384 display ram ? four windows font osd with bordering / shadow ? supports bit - mapped based osd through spi (TW8833 s only) image processing ? high quality scaler with both up/down and nonlinear scaling support ? built - in 2d de - interlacing function ? programmable hue, brightness, saturation, co ntrast and peaking ? supports programmable cropping of input video and graphics ? independent rgb gain and offset controls ? panorama / water - glass scaling ? programmable 10 - bit gamma correction for each color ? operated in frame sync mode ? black/white stretch clock generation ? spread spectrum clock ? modulation frequency and spread width are selectable power management ? supports functional based independent power down control. ? 1.8 / 3.3 v operation miscellaneous ? supports 2 - wire serial bus interface ? built - in single led back light controller ? built - in vcom dc voltage ? built - in vcom analog amplitude ? built - in dc - dc convertor ? single 27mhz crystal ? 48 pin qfn package
TW8833/TW8833s C tft display controll er intersil|techwell 7 rev a 10/25 /2010 f unctional block diagram 2d - comb video decoder scaler image enhance input controller font osd output formatter tcon triple dac s 2 - wire serial bus spi osd yin 0~2 vin tcon signals rgb out i2c_sdat i2c_sclk spi cin led/ vcom control serial data triple adcs
TW8833/TW8833s C tft display controll er intersil|techwell 8 rev a 10/25 /2010 order information package description part # name description pin co unt body size TW8833 - de na1 - gr qfn quad flat no - lead 48 7x7 mm^2 TW8833s - de na1 - gr qfn quad flat no - lead 48 7x7 mm^2
TW8833/TW8833s C tft display controll er intersil|techwell 9 rev a 10/25 /2010 functional description overview intersil| techwell?s TW8833 flat panel tv/monitor controller is a highly integrated tft panel contr oller. it integrates a high quality 2d comb ntsc/pal/secam video decoder, scalers, timing controller , triple dacs and flexible font based multi - window osd engine. this unique level of mixed signal integration turns a tft panel into a flexible display syste m. it incorporates easy - to - operate features in a single package for multi - purpose in - car lcd display, portable dvd and dvrs media players. it contains all the logic required to convert analog or digital video signals in various formats to the signal forma ts that is necessary to drive various kind of tft panel types. it supports different panel resolutions depending on the scaler and panel clock settings. it has built - in tcon for direct connecting with low cost tcon - less panel. the integrated analog front - e nd contains adcs with clamping circuits and automatic gain control (agc) circuit as well as anti - aliasing filter to minimize external component count. the built - in video decoder employs proprietary 2d comb filter y/c separation technologies to produce ex ceptionally high quality pictures. the chip's internal logic synchronizes the panel frame rate to the incoming input frame rate. a high quality image - scaling engine is used to convert the different input resolution formats to the output panel resolution. an internal de - interlacing engine also allows interlaced video to be displayed. on screen display is supported through on - chip multi - window osd engine for maximum flexibility. it also has built - in back light controller and panel bias voltage generator to further simplify the system design. the host control interface supports the standard 2 - wire serial bus analog front - end the analog front - end converts analog video signals to the required digital format. each channel contains automatic clamping circuit, a gc circuit, anti - aliasing filter and high performance adcs to minimize the external component used. the clamping circuit restores the signal dc level so it can be properly digitized. the analog inputs source selections are software programmable. different input source has different signal conditioning logics to properly convert the signal into correct format for further processing video decoder sync processor the decoder sync processor of video input detects horizontal synchronization and vertical synchroni zation signals in the composite video or in the y signal of an s - video signal. the processor contains a digital phase - locked - loop and decision logic to achieve reliable sync detection in stable signal as well as in unstable signals such as those from vcr fast forward or backward. horizontal sync processing the horizontal synchronization processing contains a sync separator, a phase - locked - loop (pll), and the related decision logic. the horizontal pll locks onto the extracted horizontal sync in all conditio ns to provide jitter free image output. from there, the pll also provides orthogonal sampling raster for the down stream processor. it has wide lock - in range for tracking any non - standard video signal. vertical sync processing the vertical sync separator d etects the vertical synchronization pattern in the input video signals. a detection window controls the determination of sync. this provides more reliable synchronization. it
TW8833/TW8833s C tft display controll er intersil|techwell 10 rev a 10/25 /2010 simulates the functionality of a pll without the complexity of a pll. the field s tatus is determined at vertical synchronization time based on the vertical and horizontal sync relationship. color decoding y/c separation the color - decoding block contains the luma / chroma separation for the composite video signal and multi - standard col or demodulation. for ntsc and pal standard signals, the luma / chroma separation can be done either by comb filter or notch/band - pass filter combination. for secam standard signals, only notch/band - pass filter is available. the default selection for ntsc/p al is comb filter. the characteristics of the band - pass filter can be found in the filter curve section. in the case of comb filter, the decoder separates luma (y) and chroma (c) of a ntsc/pal composite video signal using a proprietary adaptive comb algori thm. it leads to good y/c separation with small cross luma and cross color at both horizontal and vertical edges. due to the line buffer used in the comb filter, there is always two lines processing delay in the output images no matter what standard or fil ter option is chosen. color demodulation the color demodulation for ntsc and pal standard is done by quadrature mixing the chroma signal to the base band and extracting the chroma components with low - pass filter. the low - pass filter characteristic can be s elected for optimized transient color performance. for the pal system, the pal id or the burst phase switching is identified to aid the pal color demodulation. the secam color demodulation process consists of bell filtering, fm demodulator and de - emphasis filtering. the chroma carrier frequency is identified in the process and used to control the secam color demodulation. the sub - carrier signal for use in the color demodulator is generated by direct digital synthesis pll that locks onto the input sub - carrie r reference (color burst). this arrangement allows any sub - standard of ntsc and pal to be demodulated easily. automatic chroma gain control the automatic chroma gain control (acc) compensates for reduced amplitudes caused by transmission loss in video sign al. in the ntsc/pal standard, the color reference signal is the burst on the back porch. this color - burst amplitude is calculated and compared to standard amplitude. the chroma (cx) signals are then compensated in amplitude accordingly. the range of acc co ntrol is C 6db to +24db. low color detection and removal for low color amplitude signals, black and white video, or very noisy signals, the color will be killed. the color killer uses the burst amplitude measurement to switch - off the color when the measur ed burst amplitude falls below a programmed threshold. the threshold has programmed hysteresis to prevent oscillation of the color killer operation. this function can be disabled by programming a low threshold value. automatic standard detection the video decoder has its automatic standard discrimination circuitry. the circuit uses burst - phase, burst - frequency and frame rate to identify ntsc, pal or secam color signals. the standards that can be identified are ntsc (m), ntsc (4.43), pal (b, d, g, h, i), pal (m), pal (n), pal (60) and secam (m). each standard can be included or excluded in the standard recognition process by software control. the identified standard is indicated by the standard selection (sdt) register. automatic standard detection can be ove rridden by software controlled standard selection. video format support the integrated video decoder supports all common video formats as shown in table 1. it needs to be programmed appropriately for each of the composite video input formats.
TW8833/TW8833s C tft display controll er intersil|techwell 11 rev a 10/25 /2010 format lines fields fsc country ntsc - m 525 60 3.58 mhz u.s., many others ntsc - japan (1) 525 60 3.58 mhz japan pal - b, g, n 625 50 4.43 mhz many pal - d 625 50 4.43 mhz china pal - h 625 50 4.43 mhz belgium pal - i 625 50 4.43 mhz great britain, othe rs pal - m 525 60 3.58 mhz brazil pal - cn 625 50 3.58 mhz argentina secam 625 50 4.406mhz 4.250mhz france, eastern europe, middle east, russia pal - 60 525 60 4.43 mhz china ntsc (4.43) 525 60 4.43 mhz transcoding table 1. video input formats supported notes: (1). ntsc - japan has 0 ire setup. component processing luminance processing the video decoder adjusts brightness by adding a programmable value (in register brightness) to the y signal. it adjusts the picture contrast by changing the gain (in regist er contrast) of the y signal. it also provides a sharpness control function through a control register. the center frequency of the peaking filter is selectable. a coring function is provided along with the sharpness control to reduce enhancement to the no ise. the hue and saturation when decoding ntsc signals, the decoder can adjust the hue of the chroma signal. the hue is defined as a phase shift of the subcarrier with respect to the burst. this phase shift can be programmed through a control register. the color saturation can be adjusted by changing the gain of cb and cr signals for all ntsc, pal and secam formats. the cb and cr gain can be adjusted independently for flexibility.
TW8833/TW8833s C tft display controll er intersil|techwell 12 rev a 10/25 /2010 input image control the input cropping control provides a way for programmin g the active display window region for the selected input video or graphic. in the normal operation, the first active line starts with the vsync signal. this and vertical active length register setting are used to determine the active vertical window. the active pixel starts hsync. this and the horizontal active width register are used to determine the active horizontal window. the vertical window is programmed in line increments. the horizontal window is programmed in one pixel increments for single pixel input mode or two pixels increments for double pixels input mode. if data qualifier is used, then only qualified pixels will be counted in the window size. image scaling the internal high quality image - scaling engine can scale up or down the input image to fit the output panel resolution. it operates in the frame - sync mode such that both input and output frame rates are always the same. the vertical and horizontal scaling ratio can be adjusted independently in fine granularity. the panel clock frequency sel ection needs to be coordinated with the scaling ratio as well as input frequency to avoid internal buffer overrun. the scaler also acts as a de - interlacer to properly de - interlace the input video based on its field nature. the scaler can also be programmed to perform the panorama or water glass mode scaling for flexible display output. in addition, the image mirroring can be supported through scaler with register control. image enhancement processing black/white stretch this feature is to expand dynamic ran ge of the input image, which creates more vivid image impression. tft panel support it supports a variety of active matrix tft panel types and resolutions. dithering it has the dithering circuit to reduce the output dynamic range to fit the panel type. th is allows lcd panels with 4, 6 or 8 bits per color per pixel to display up to 16.8 million colors and lcd panels with 3 bits per color per pixel to can display up to 2.1 million colors. it employs both spatial and frame modulation dithering. when dithering with the least significant 4 - bits of input data it uses spatial modulation with 4x4 blocks of pixels. when dithering with the least significant 1 to 3 bits of input data, it uses either spatial modulation with 2x2 pixel blocks, or frame modulation. gamma table it has integrated gamma table for each color output and it is fully programmable through host bus. tcon the integrated timing controller supports flexible column/row driver control signals to interface with tcon - less panel directly.
TW8833/TW8833s C tft display controll er intersil|techwell 13 rev a 10/25 /2010 font on screen display the tw883 3 supports built - in osd controller with programmable ram font. the osd display is independent of the input active window setting or the scaling ratio. the on - chip osd controller is a character - based controller. the pre - defined character o r graphic bit map is stored in the font ram. it can store up to 256 fonts. each character is 12 pixels wide by 18 pixels high. the characters can be displayed on the screen in four user defined window locations of any size from 1 to 384 characters. the spa ces between characters are also programmable. there is a limit of 384 characters that may be displayed on screen at one time in all windows combined. the attributes of each window can also be set to give it a shadow effect or 3 - d effect . in addition, the characters can be expanded by a factor of 2,3 or 4 in vertical or horizontal directions and have the blinking effect, italic effect , under line effect and border/shadow effect on a character by character basis. on chip osd functions % font sram : max 256 user programmable single color font (6912x8 sram) ? % character register sram : 384 location (8 - bit font address + 12 - b it character attribute, 384x20 sram) ? % characters character color : 16 colors character background color : 16 colors character blinking : enable/disable, 1 hz blinking frequency character italic effect : enable/disable character under line effect : enable/disable character border/shadow effect : enable/disable (multi osd window display case : chip has a limitation) character space : both h and v programmable by number of pixels quick character change in window : programmable start address and buffer size programmable osd color palette support re - designed osd font supporting standard alpha - numerical character set % windows number of windows : 4 independent windows window color : 16 colors window zoom : 2, 3, 4 times zoom by dot number , h/v separate zooming control window position : programmable h direction : 1 - pixel per step, v direction : 1 - line per step wi ndow size : both h and v programmable by number of characters window border ing/shadowing effect : 4 independent windows enable/disable control window alpha blending control : 4 independent windows control ? 16 different color for alpha blending support(4 - b it control) window 3 - d effect : 4 independent windows enable/disable control window border color : 16 colors window border width : programmable
TW8833/TW8833s C tft display controll er intersil|techwell 14 rev a 10/25 /2010 basic register setting flow example for built - in osd controller step_1: osd_window_configuration setting for window#1 (0x310~0x31f) note) window#2 (0x320~0x32f), window#3 (0x330~0x33f), window#4 (0x340~0x34f) 1. osd window disable 0x 310 , bit7 2. o sd window zoom multiplier 0x310, bit1 - 0: v, bit3 - 2:h 3. osd window background b color 0 x31e, bit6 - 4 4. osd window background g color 0x31e, bit6 - 4 5. osd window background r color 0x31e, bit6 - 4 6. osd window background color extension 0x31e, bit7 osd window 3 - d effect top/bottom mode select 0x31b, bit6 8. osd window 3 - d effect level select 0x31b, bit5 9. osd window 3 - d effect enable/disable 0x31b, bit7 10. osd window h - start location (see details in next page) 0x313, bit7 - 0 0x312, bit6 - 4 11. osd window v - start location (see details in next page) 0x314, bit7 - 0 0x312, bit1 - 0 12. osd window width 0x316, bit5 - 0 13. osd window height 0x315, bit5 - 0 14. osd window border_line width 0x318, bit4 - 0 15. osd window border_line b color 0x317, bit2 - 0 16. osd window border_line g color 0x317, bit2 - 0 17. os d window border_line r color 0x317, bit2 - 0 18. osd window border_line enable 0x318, bit7 19. osd window border color extension 0x317, bit3 20. osd window shadow width 0x31c, bit4 - 0 21. osd window shadow b color 0x31b, bit2 - 0 22. osd window s hadow g color 0x31b, bit2 - 0 23. osd window shadow r color 0x31b, bit2 - 0 24. osd window shadow enable 0x31c, bit7 25. osd window shadow color extension 0x31b, bit3 26. osd window h - space width (between border_line and characters) 0x319, bit6 - 0 27. osd window v - space width (between border_line and characters) 0x31a, bit6 - 0 28. character h - space width (between character and character) 0x31d, bit7 - 4 0x31c, bit6 29. character v - space width (between character and character) 0x31d, bit3 - 0 0x31 c, bit5 30. osd window alpha blending color select 0x311, bit7 - 4 31. osd window alpha blending value control 0x311, bit3 - 0 32. window content star t address 0x305, bit0 0x306, bit7 - 0 33. repeat 1 C 32
TW8833/TW8833s C tft display controll er intersil|techwell 15 rev a 10/25 /2010 step_2: osd_color_attribute / font s etting (osd ram) 1. enable osd ram access - 0x304 (bit0 = 0) 2. osd ram address - 0x305 (bit0), 0x306 (bit7 - 0) - the first address is step_1_32 window content start address. 3. osd ram data port high ( font address ) - 0x307 data is writte n to above address automatically. - 0x 307 =8 ? hfe : font_ram h00 to hff ( max 256 characters) 4. osd ram data port bit1 9 ( border effect ), bit18( under line effect ) , bit17( italic effect ), bit1 6 ( blinking effect ) - 0x 304 bit7, bit6, bit5, bit4 data is written to above address automatically. 5. osd ram data port low ( color attribute ) - 0x308 data is written to above address automatically. 6. repeat 2), 3), 4) , 5) . - the address should be increased by one each. step_3: color look - up table setting 1. select color look - up table write address - 0x30c (bit[3:0]) - bit[3:0] : these 4 bits specify one of the 16 entries in the look - up table. each entry is a 16 - bit rgb color by its content. - there are 65536 colors available; but only s ixteen of them are accessible by osd controller at a given time. bit[3:0] default value 0000 0000h 0001 0010h 0010 0400h 0011 0410h 0100 8000h 0101 8810h 0110 8400h 0111 8410h 1000 2104h 1001 0008h 1010 0200h 1011 0208h 1100 4000h 1101 4008h 1110 4200h 1111 ffffh 2 . color look - up table control bits setting - 0x30d (high byte), 0x30e (low byte) - the data of the look - up table is accessed through 0x30d and 0x30e. 3. repeat 1), 2) to program each entry of the look - up tabl e .
TW8833/TW8833s C tft display controll er intersil|techwell 16 rev a 10/25 /2010 step_4: font_ram_data setting (font ram) 1. enable font ram access - 0x 30 4 (bit0 = 1) 2 . font ram address setting - 8 bits (h00 C h ff ) - 0x 30 9 - h00~h ff : single font ram( 256 programmable characters) 3. font ram d ata port - 0x 30 a data is written to above address automatically. 4. repeat ( 4) at 27 times for one font ram data - t he internal address automatically increases by one each. 5. new font ram address setting C 8 bits 6 . repeat 3),4),5) - the font ram address should be increased by one each. note) as for the font ram configuration and font bit mapping, see the detailed description step_5: end of osd setting and enable osd 1. osd on/off enable control 0: on, 1: off - 0x 30c ( bit4 = 0) 2. osd window enable - 0x 310 (bit7 = 1) window1 enable
TW8833/TW8833s C tft display controll er intersil|techwell 17 rev a 10/25 /2010 osd window start location: built - in osd controller o internal generated osd de position delayed from h - sync: 0x303[7:0] . o osd window h_start location from start of internal osd de: 0x 312 [ 6 : 4 ] , 0x 313[7:0] increment by 1 pixel at a time . o osd window v_start location from start of vact: 0x 312 [1:0] , 0x 314[7:0] increment by 1 line at a tim e . 0 1 2 0 19 address the characters can be displayed on the screen in four user defined window locations of any size from 1 to 384 characters. th ere is a limit of 384 characters that may be displayed on screen at one time in all windows combined. example window #1: address 0 C C C osd_ram configuration 381 382 383 19 0 8 7 font_address ( 12 - bits) bit 19: border/shadow bit 18: under line effect on bit 17: italic effect on bit 16: blinking bit 15 - 8: font address font_attribute (8 - bits) bit 7: character?s background color extension bit 6: character?s background r bit 5: character?s background g bit 4: character?s background b bit 3: character?s color extension bit 2: character r bit 1: character g bit 0: character b
TW8833/TW8833s C tft display controll er intersil|techwell 18 rev a 10/25 /2010 alpha blending for osd window the tw883 3 uses "alpha blending" in osd 4 separation windows & 16 separation colors . alpha blending mixes (adds) the video signal and osd signal at the following specified levels. in other words, alpha blending determines the transparency of the osd window each color to in relation to video sig nal. when alpha blending is disabled , the only osd data is displayed in osd window. the alpha blending level selection are 4 - bit assigned, it can support 8 different level control s . the alpha blending level bits and alpha blending color selection bit s ar e in register 0x 311 for window #1, 0x321 for window#2, 0x331 for window#3, 0x341 for window#4. alpha[3:0] video level 0000 0.00 % 0001 12.5 0010 25.0 0011 37.5 0100 50.0 0101 62.5 0110 75.0 0111 87.5 1000 100 alpha blending concept x + video level vie vel osd data video data x 1 C video level
TW8833/TW8833s C tft display controll er intersil|techwell 19 rev a 10/25 /2010 spi on s creen display ( f or TW8833s only) the integrated spiosd provides a flexible mapping between its display on the lcd and its bit mapped image stored in the spi memory. in general a buffer in the spi memory is specified for the image to be displayed. the bu ffer size is larger than the display size of the window. the bit mapped image stored is 8 bits per pixel. during display, the 8 - bit pixel is fetched from the spi memory and mapped to a 32 - bit quantity by the window?s lut (look up table). the 32 - bit quan tity consists of 24 - bit rgb, 7 - bit alpha blending attribute, and one bit blinking attribute. the pixel is then mixed with video before displaying on the lcd panel. two spiosd windows are provided. each window has its own set of register but shares a lut. both windows can be active at the same time but cannot be overlapped and have a minimum horizontal spacing requirement. looping control for adjacent buffers is provided for each window. animation can be achieved by properly allocating multiple buffers i n the adjacent area and the looping control. spiosd window display starting location and sizes there are four registers used to specify the staring location and size on the lcd: ? window i horizontal start ? window i vertical start ? window i horizontal l ength ? window i vertical length
TW8833/TW8833s C tft display controll er intersil|techwell 20 rev a 10/25 /2010 spiosd window buffer memory three registers together define the buffer starting location and boundaries: ? window i buffer memory starting address ? window i buffer memory horizontal length ? window i bu ffer memory vertical length two registers point to the starting location of the image stored: ? window i image vertical start ? window i image horizontal start
TW8833/TW8833s C tft display controll er intersil|techwell 21 rev a 10/25 /2010 spiosd window loop control three registers are used for l oop control: ? window i looping horizontal frame number ? window i looping vertical frame number ? window i frame duration in the diagram below, the looping horizontal frame number register contains a value n, and the looping vertical frame number register con tains a value m. the display starts from frame #00 and then moves horizontally to the right and then vertically down. the display order is #00, #01, #02 , 0n, #10, #11, #12, #1n, . #m0, #m1, #mn. each frame stays on for the time specified by frame duration register.
TW8833/TW8833s C tft display controll er intersil|techwell 22 rev a 10/25 /2010 osd display path in normal mixing order, video input is mixed with font osd first. the resultant output is then mixed with spiosd. alternatively, video input can be mixed with spiosd first and the n font osd.
TW8833/TW8833s C tft display controll er intersil|techwell 23 rev a 10/25 /2010 microcontroller interface the host interface is accessed via 2 - wire serial bus interface. it always operates as a slave device. two wire serial bus interface figure 1 . d efinition of the serial bus interface bus start and stop figure 2. one complete register write sequence via the serial bus interface mc_sd a start condition st op condition mc_scl k mc_scl k device id (1 - 7) r/w index (1 - 8) data (1 - 8) mc_sda start condition stop condition ack ack ack
TW8833/TW8833s C tft display controll er intersil|techwell 24 rev a 10/25 /2010 figure 3 . one complete register read sequence via the serial bus interface the two wire serial bus interface is used to allow an external micro - controller to write control data to, and read control or other information from the internal registers. mc_sclk is the serial clock and mc_sda is the data line. both lines are pulled high by resistors connected to vdd. i c s communicate on the bus by pulling mc_sclk and mc_sda low through open drain outputs. in normal operation the master generates all clock pulses, but control of the mc_sda line alternates back and forth between the master and the slave. for both read and write, each byte is transferred msb first, and the data bit is valid whenever mc_sclk is high. the device is operated as a bus slave device . the 7 - bit device address field is fixed and concatenated with the read/write cont rol bit to form the first byte transferred during a new transfer. if the read/write control bit is high the next byte will be read from the slave device. if it is low the next byte will be a write to the slave. when a bus master (the host microprocessor) d rives mc_sda from high to low, while mc_sclk is high, this is defined to be a start condition (see figure 1 .). all slaves on the bus listen to determine when a start condition has been asserted. after a start condition, all slave devices listen for their d evice addresses. the host then sends a byte consisting of the 7 - bit slave device id and the r/w bit. this is shown in figure 2 . (the next byte is normally the index to the internal registers and is a write to the device therefore the first r/w bit is norma lly low.) after transmitting the device address and the r/w bit, the master must release the mc_sda line while holding mc_sclk low, and wait for an acknowledgement from the slave. if the address matches the device address of a slave, the slave will respond by driving the mc_sda line low to acknowledge the condition. the master will then continue with the next 8 - bit transfer. if no device on the bus responds, the master transmits a stop condition and ends the cycle. notice that a successful transfer always i ncludes nine clock pulses. to write to the internal register, the master sends another 8 - bit of data, it loads this to the register pointed by the internal index register. the device will acknowledge the 8 - bit data transfer and automatically increment th e index in preparation for the next data. the master can do multiple writes if they are in ascending sequential order. after each 8 - bit transfer the device will acknowledge the receipt of the 8 - bits with an acknowledgement pulse. to end all transfers, the host has to issue a stop condition. re - start condition mc_sclk device id (1 - 7) r/w index (1 - 8) mc_sda ack ack data (1 - 8) stop condition nack start condition device id (1 - 7) r/w ack
TW8833/TW8833s C tft display controll er intersil|techwell 25 rev a 10/25 /2010 serial bus interface 7 - bit slave address read/write bit 1 0 0 0 1 1 0 1=read 0=write table 2. serial bus interface 7 - bit slave address and read write bit the device read cycle has two phases. the fi rst phase is a write to the internal index register. the second phase is the read from the data register. (see figure 3 ). the host initiates the first phase by sending the start condition. it then sends the slave device id together with a 0 in the r/w bit position. the index is then sent followed by either a stop condition or a second start condition. the second phase starts with the second start condition. the master then resends the same slave device id with a 1 in the r/w bit position to indicate a read. the slave will transfer the contents of the desired register. the master remains in control of the clock. after transferring eight bits, the slave releases and the master takes control of the mc_sda line and acknowledge the receipt of data to the slave. t o terminate the last transfer the master will issue a negative acknowledge (mc_sda is left high during a clock pulse) and issue a stop condition. parameter symbol min typ max units bus free time between stop and start t bf 740 - - ns mc_ sda setup time t ssdat 74 - - n s mc_ sda hold time t hsdat 50 - 900 ns setup time for start condition t ssta 370 - - ns setup time for stop condition t sstop 370 - - ns hold time for start condition t hsta 74 - - ns rise time for mc_ sclk and mc_ sda t r - - 300 ns table 3. serial bus interface timing serial bus interface timing stop start stop start mc_sda mc_sclk t bf t hsta t sstop t ssta t ssdat t r t f t hsdat data
TW8833/TW8833s C tft display controll er intersil|techwell 26 rev a 10/25 /2010 pin diagram * for TW8833s only vss33 vss18 vdd18 tclrl / sd7 trclk / sd6 trudl / sd5 tclp / sd4 tcspr / sd3 trspb / sd2 troe / sd1 tcspl / sd0 vdd33 vdde rout gou t bout avdda avdda5 vcom_amp vcom_dc dcdcs leds dcdcp / svs ledp pwm1 vd[1] nc vss vd[2] vd[3] vd[4] vd[5] vd[6] TW8833/TW8833s s 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 avsda avsad yin2 yin1 yin0 cin0 vin0 avdad avspll avdpll vss18 vdd18 rstb gpo sda scl spics / gpo3 spidi1*/ gpo2* spidi0 / gpo1 spick / gpo0 xti xto tcclk / sclk trspt / shs
TW8833/TW8833s C tft display controll er intersil|techwell 27 rev a 10/25 /2010 pin description this section provides a detailed description of each pin for the TW8833. the pins are arranged in functional groups according to their associated interface. the active state of the signal is determined by the trailing symbol at the end of the signal name. a "#" symbol indicates that the signal is active or asserted at a low voltage level. when "#" is not present after the signal name, the signal is active at the high voltage level. the pin description also includes the buffer direction and type used for that pin. pin# i/o pin name description internal connection rec ommended connection of unused pin status at hw reset analog i/f signals and power 2 p avsad analog a/d ground - - pwr 3 ai yin2 analog composite or luma input 2 connect to avsad - 4 ai yin1 analog composite or luma input 1 5 ai yin0 analog compos ite or luma input 0 6 ai cin0 analog component c input 0 7 ai vin0 analog component v input 0 8 p avdad analog a/d power +1.8v - pwr 9 p avspll pll (internal analog) ground pwr 10 p avdpll pll (internal analog) power +1.8v 40 ai leds l ed sense connect to avsad hi - z 41 ai dcdcs dcdc sense 42 ao vcom_dc vcom out for dc - - 43 ao vcom_amp vcom out for amp tcon - column driver inversion dac i/f signals and power 44 p avdda5 dac analog power +5.0v - - pwr 45 p avdda dac an alog power +3.3v 46 ao bout dac analog blue data output open/unconnected - 47 ao gout dac analog green data output 48 ao rout dac analog red data output 1 p avsda dac analog ground - pwr digital i/f signals 13 i rstb# reset pin pull up - - 14 o gpo general purpose data out pull up 15 i/o sda i2c data - open/unconnected - 16 i scl i2c clock
TW8833/TW8833s C tft display controll er intersil|techwell 28 rev a 10/25 /2010 17 o spics spi chip select - * open/unconnected - o gpo 5 gpo5 18 i/o spidi1 spi data 1 (for TW8833s only) o gpo2 gpo2 (for TW8833s only) 19 i/o spidi0 spi data 0 o gpo1 gpo1 20 o spick spi clock o gpo0 gpo0 21 i xti crystal terminal or oscillator input - - - 22 o xto crystal terminal 23 o tcclk tcon - column driver clock pull down open/unconnected hi - z o sc lk serial clock 24 o trspt tcon - row driver starting pulse(top start) o shs serial hsync 26 o tcspl tcon - column driver start pulse (left to right scan) o sd0 serial data output bit (lsb) 27 o troe tcon - row driver output enable o s d1 serial data output bit 28 o trspb tcon - row driver starting pulse (bottom start) o sd2 serial data output bit 29 o tcspr tcon - column driver start pulse (right to left scan) o sd3 serial data output bit 30 o tclp tcon - column driver l oad pulse o sd4 serial data output bit 31 o trudl tcon - up down selection o sd5 serial data output bit 32 o trclk tcon - row driver shift clock o sd6 serial data output bit 33 o tclrl tcon - left right election o sd7 serial data output bit (msb) 37 o pwm1 pwm control 1 - * open/unconnected - 38 o ledp led control pulse 39 o dcdcp dcdc pulse o svs serial vsync digital power 25 p vdd33 digital i/o power +3.3v - - pwr 36 p vss33 digital i/o ground
TW8833/TW8833s C tft display controll er intersil|techwell 29 rev a 10/25 /2010 12,34 p vdd18 digital core power +1.8v 11,35 p vss18 digital core ground 1: pull - up resistor 38k(min), 54k(typ), 83k(max)ohm 2: pull - down resistor 35k(min), 57k(typ), 107k(max)ohm 3: - means n/a 4: _* means register controllable after reset
TW8833/TW8833s C tft display controll er intersil|techwell 30 rev a 10/25 /2010 par ametric information ac/dc electrical parameters table 4 . absolute maximum ratings parameter symbol min typ max units v dda 5 *(measured to v ssa *) 5 v vdda 5 m - - 5.25 v v dda33 *(measured to v ssa *) 3.3v vdda 33 m - - 3.6 v v dda18 * (measured to v ssa18 *) 1 .8v vddam - - 1.92 v v dd18 * (measured to v ss18 * ) 1.8v vdd 18 m - - 1.98 v v dd33 (measured to v ss33 ) 3.3v vdd 33 m - - 3.6 v voltage on any digital signal pin (see the note below) - v ss33 C 0.5 - 5.5 v analog input voltage (supplied by 1.8v) - v ssa18 C 0.5 - 1.92 v analog input voltage (suppied by 3.3v) - v ssa - 0.5 3.6 v analog input voltage (suppied by 5 v) - v ssa - 0.5 3.6 v storage temperature t s C 65 - +150 c junction temperature t j - - +125 c reflow soldering tpeak 255 +5/ - 0 (10~30 seconds) c n ote * : v dda 5 : avdda5 v dda33 : avdda v ssa : avsda v dda18 : avdad, avdpll v ssa18 : avsad, avspll v dd33 : vdd33 v ss3 3 v ss 33 v dd18 : vdd18 v ss18 : vss18 note: stresses above those listed may cause permanent damage to the device. this is a stress rating only , and functional operation at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect device reliability. this device employs high - impedance cmos devices on all signal pins. it must be handled as an esd - sensitive device. voltage on any signal pin that exceeds the ranges list in table 4 can induce destructive latch - up.
TW8833/TW8833s C tft display controll er intersil|techwell 31 rev a 10/25 /2010 table 5 . characteristics parameter symbol min typ ma x units supply power supply io 3.3v v dd33 3.15 3.3 3.6 v power supply digital core 1.8v v dd18 1.62 1.8 1.98 v power supply analog 5v v dda5 - - 5.25 v power supply analog 3.3v v dda33 3.15 3.3 3.6 v power supply analog 1.8v v dda18 1.62 1.8 1. 92 v ambient operating temperature t a - 40 + 85 c analog supply current 5v iaa5 - 11.5 - ma analog supply current 3.3v iaa33 - 4.8 - ma analog supply current 1.8v (cvbs) iaa18 - 25.1 - ma digital i/o supply current 3.3v* idd33 - 8.9 - ma digital cor e supply current* idd18 - 41.3 - ma * note : digital i/o and core power supply current measurement is base on w q vga output ( 10 mhz clock rate ) with smpte pattern. parameter symbol min typ max units digital inputs input high voltage (ttl) v ih 2.0 - - v input low voltage (ttl) v il - - 0.8 v input high voltage (xti) v ih 2.0 - v dd33 + 0.5 v input low voltage (xti) v il - - 0.8 v input high current (v in =v dd ) i ih - - 10 ? in =vss) i il - - C ? in =2.4 v) c in - 5 - pf digital outputs output high voltage (i oh = C oh 2.4 - v dd33 v output low voltage (i ol = 4ma) v ol - 0.2 0.4 v 3 - state current i oz - - 1 0 ? o - 5 - pf
TW8833/TW8833s C tft display controll er intersil|techwell 32 rev a 10/25 /2010 parameter symbol min typ max units analog input analog pin input voltage vi - 1 - vpp yin0, yin1 and yin2 input range (ac coupling required) 0.5 1.0 2.0 vpp cin0 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp vin0 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp analog pin input capacitance c a - 7 - pf adcs adc resolution adcr - 9 - bits adc integral non - linearity ainl - ? 1 - lsb adc differential non - linearity adnl - ? 1 - lsb adc clock rate f adc - 27 60 mhz video bandwidth ( - 3db) bw - 10 - mhz parameter symbol min typ max units horizontal pll line frequency (50hz) f ln - 15.625 - khz line frequency (60hz) f ln - 15.734 - khz static deviation ? f h - - 6.2 % subcarrier pll subcarri er frequency (ntsc - m) f sc - 3579545 - hz subcarrier frequency (pal - bdghi) f sc - 4433619 - hz subcarrier frequency (pal - m) f sc - 3575612 - hz subcarrier frequency (pal - n) f sc - 3582056 - hz lock in range ? f h ? 450 - - hz crystal spec nominal frequency (fundamental) - 27 - mhz deviation - - ? 50 ppm load capacitance cl - 20 - pf series resistor rs - 80 - ohm *note : crystal deviation crossover normal operation temperature range
TW8833/TW8833s C tft display controll er intersil|techwell 33 rev a 10/25 /2010 filter curves anti - alias filter decimation filter 0 2 4 6 8 10 12 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10 7 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db)
TW8833/TW8833s C tft display controll er intersil|techwell 34 rev a 10/25 /2010 chroma ba nd pass filter curves luma notch filter curve for ntsc and pal pal/seam ntsc ntsc pal 0 1 2 3 4 5 6 7 8 9 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) 0 1 2 3 4 5 6 7 8 x 10 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 frequency (hertz) gain (db)
TW8833/TW8833s C tft display controll er intersil|techwell 35 rev a 10/25 /2010 chrominance low - pass filter curve lo w med high cbw=0 cbw=3 cbw=1 cbw=2 0 1 2 3 4 5 6 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db)
TW8833/TW8833s C tft display controll er intersil|techwell 36 rev a 10/25 /2010 mechanical data 48 qfn
TW8833/TW8833s C tft display controll er intersil|techwell 37 rev a 10/25 /2010 notes: 1. all dimensions are in millimeters. symbol millimeter inch min nom max min nom max a 0.80 0.85 0.90 0.031 0.033 0.035 a1 0.00 0.02 0.05 0.000 0.001 0.002 a2 0.60 0.65 0.70 0.024 0.026 0.028 a3 0.2 ref. 0.008 ref. b 0.18 0.25 0.30 0.007 0.010 0.012 d/e 6 .90 7.00 7.10 0.272 0.276 0.280 d1/e1 6.75 bsc. 0.266 bsc. d2/e2 4.45 4.60 4.75 0.175 0.181 0.187 l 0.30 0.40 0.50 0.012 0.016 0.020 e 0.50 bsc. 0.020 bsc. ? ? ? ? ? * controlling dimension : mm
TW8833/TW8833s C tft display controll er intersil|techwell 38 rev a 10/25 /2010 register summary the registers are organized in functional groups in this register summary. a register containing different functional bits may appear more than once in different functional groups. if a particular bit of a register is not related to that functional group, i t is printed in smaller font than those related. for example, bit 7 of index 006 is classified as general and is printed in normal size; the other bits in this register are printed in smaller size for their functionality is not classified as general. - : for register it means reserved, for reset value it means unknown general index (hex) 7 6 5 4 3 2 1 0 reset value 000 id rev 30 h x ff - page 0 0h general index (hex) 7 6 5 4 3 2 1 0 reset value 002 int7 int6 int5 int4 int3 int2 int1 int0 21h 003 imask ff h 006 srst - ainc tckdiv trud l tclr l trsp tcsp 00h 007 - tconsel 00h 008 tckdrv - tri_en gpo_sel 3 0h 009 gpoen2 - gpo 5 - gpo2 gpo1 gpo0 00h 01f test 00h
TW8833/TW8833s C tft display controll er intersil|techwell 39 rev a 10/25 /2010 ledc /dc - dc/vcom control index (hex) 7 6 5 4 3 2 1 0 reset value 0db - fpclk_ delay fpwm2[9 - 8] fpwm1[9 - 8] 05h 0dc fpwm1 [7 - 0] 00 h 0dd dpwm1 80 h 0de fpwm2 [7 - 0] 00 h 0df dpwm2 80 h 0e0 l_oven l_oien l_uien l_fben - leda_pd ledc_en f2h 0e1 leda_fb leda_vop 77 h 0e2 - ledc_st ledc_lstp 04h 0e3 ledc_ fpwm 4 0h 0e4 ledc_ fdim 84h 0e5 d mode ledc_ ddim 00h 0e6 ledc_ pwmtop 2 0h 0e8 d_oven d_oien d_uien d_fben - leda_pd dc_en f2h 0e9 - dc_fb dc_vop 0ah 0ea - dc_st dc_lstp 04h 0eb dc_fpwm 4 0h 0ec dc_pwmtop 20 h 0ed vcom _offset 8 0h 0ee - iref vcom_amp 2 0h dac index (hex) 7 6 5 4 3 2 1 0 reset value 0f 0 dac _ pd dac_vcm dacgain c8 h 0f1 - dac_cki nv dac_ck dly dactog dacinv 02h sspll index (hex) 7 6 5 4 3 2 1 0 reset value 0f6 spiclk_div pclk_div 00 0f7 - edge_s el_p cp_x4_sspll_p lp_x4_sspll_p lp_x8_sspll_p 16h 0f 8 - fpll[19:16] 01 h 0 f 9 fpll[ 15:8] 2 0h 0f a fpll [7:0] 00h 0f b fss [7:0] 40 h 0f c pd_sspl l ssd ssg 30 h 0f d post vco - ipmp 11h
TW8833/TW8833s C tft display controll er intersil|techwell 40 rev a 10/25 /2010 decoder index (hex) 7 6 5 4 3 2 1 0 reset value 101 vdloss hlock slock field vlock - mono det50 - 102 - fc27 ifsel ysel csel0 vsel 40h 1 03 - - 1 04 - ckhy - 00h 105 - save - fbpy fbpc fbpv dec_sel 00h 106 sreset iref vref agc_en clkpdn y_pdn c_pdn v_pdn 00h 107 vdelay_hi vactive_hi hdelay_hi hactive_hi 12h 108 vdelay_lo 12h 109 vactive_lo 2 0h 10a hdelay_lo 0a h 10b hactive_lo d0h 10c pbw dem palsw set7 comb hcomp ycomb pdly cch 10d - wssen ccoddline 00 h 110 brightness 00h 111 contrast 5ch 112 scurve vsf cti sharpness 11h 113 sat_u 80h 114 sat_v 80h 115 hue 00h 117 shcor - vshp 80 h 118 ctcor ccor vcor cif 44h 11a - eds_en cc_en parit y ff_ovf ff_emp cc_eds lo_hi 1 0h 11b cc_data - 11c dtstus stdnow atreg standard 27h 11d start pal60 palcn palm ntsc4 secam palb ntscm 7fh 11e - cvstd cvfmt 00 h 11f test 00h 120 clpend clpst 50h 121 nmgain wpgain agcgain8 2 2h 122 agcgain f0h 123 pe akwt d8h 124 clmpld clmpl bch 125 synctd synct b8h 126 misscnt hswin 44h 127 pclamp 38 h 128 vlcki vlcko vmode detv afld vint 00h 129 bsht vsht 00h 12a ckillmax ckillmin 78h 12b fcomb htl vtl1 vtl 44h 12c cklm ydly hflt 30h 12d hplc evcnt palc sde t tbc_en bypass syout hadv 14h
TW8833/TW8833s C tft display controll er intersil|techwell 41 rev a 10/25 /2010 12e hpm acct spm cbw a5h 12f nkill pkill skill cbal fcs lcs ccs bst e0h 130 sid_fail pid_fail fsc_fail slock_f ail csbad mvcsn cstripe ctype - 131 vcr wkair wkair1 vstd nintl wssdet edsdet ccdet - 132 hfref/gval/pherrdo/c gaino/bampo/minavg/sythrd/syamp - 133 frm ynr clmd psp 05h 134 index nsen/ssen/psen/wkth 1ah 135 ctest yclen cclen vclen gtest vlpf ckly cklc 00h 140 - wss0 - 141 crcerr wssfld wss1 - 142 wss2 -
TW8833/TW8833s C tft display controll er intersil|techwell 42 rev a 10/25 /2010 scaler / tcon index (hex) 7 6 5 4 3 2 1 0 reset valu e 201 mirror pwen pxdbl lndbl lnext lnfix valock smode 00 h 202 - foffset 2 0h 203 xscale[7 - 0] 0 0h 204 xscale[15 - 8] 2 0h 205 yscale[7 - 0] 00h 206 yscale[15:8] 2 0h 207 pxscale [11 - 4] 8 0h 208 pxinc [7 - 0] 1 0h 209 hdscale[7 - 0] 00h 20a - vanom ceven hft hds cale[11 - 8] 0 1 h 20b hdelay2 3 0h 20c hactive[7 - 0] d 0h 20d hactive2[9 - 8] ckosel ckp vsp hsp ckdiv 8 0h 20e - lntt[9 - 8] hpadj[11 - 8] 00h 20f hpadj[7 - 0] 00h 210 hapos 1 0h 211 halen[7 - 0] 0 0h 212 pxscale[3 - 0] halen[11 - 8] 03 h 213 hspos 10 h 214 pxinc[11 - 8] hslen 20h 215 vapos 20h 216 valen[7 - 0] 00h 217 pxinc[11 - 8] valen{11 - 8] 03h 218 vslen vspos 00h 219 lntt[7 - 0] 00h 21a dm_top 00h 21b dm_bot 00h 240 csp_wid csp_pos 10h 241 clp_pos 00h 242 clp_wid 01h 243 - rck_pos[10 - 8] - rck_wid[10 - 8] 00h 244 rck_pos[7 - 0] 00h 245 rck_wid[7 - 0] 01h 246 roe_ext roe_pos[10 - 8] - roe_wid[10 - 8] 00h 247 roe_pos[7 - 0] 00h 248 roe_wid[7 - 0] 01h 249 - rsp_wid rsp_pos[10 - 8] 10h 24a rsp_pos[7 - 0] 00h 24b - cpl_pos[10 - 8] clp_ext 00h 24c cpl_pos[7 - 0] 10h 24d roe_mod c pl_pol rsp_pol roe_pol rck_pol clp_pol csp_pol 80h 24e cpl_ref cpl_swp cpl_tgm roe_de clp_ref clp_de csp_de 00h
TW8833/TW8833s C tft display controll er intersil|techwell 43 rev a 10/25 /2010 image adjustment index (hex) 7 6 5 4 3 2 1 0 reset value 28 0 - hue 2 0 h 281 contrast_r 80h 282 contrast_g 80h 283 contrast_b 80h 284 con trast_y 80h 285 contrast_cb 80h 286 contrast_cr 80h 287 brightness_r 80h 288 brightness_g 80h 289 brightness_b 80h 28a brightness_y 80h 28b h_sharp_cor h_sharpness 30h 28c sh_fre q - 00h 2b0 - pedlvl whtlvl - bw_en 10h 2b1 bw_fmin 40h 2b2 bw_fmax 40h 2b6 bw_black_tilt 67h 2b7 bw_white_tilt 94h 2bf tpg_en swap pat_sel 00h gamma & dither index (hex) 7 6 5 4 3 2 1 0 reset value 2e0 gamae_ r gamae_ g gamae_ b - auto_inc gamma_rgb_indx 00 h 2e1 gamma_ram_starting_addr 00h 2e2 - gamma_ram_data[9:8 ] 00h 2e3 gamma_ram_data[7:0] 00h 2e4 - dither_option - dither_format 00h 2f0 rdpos_x[7:0] 00h 2f1 rdpos_y[7:0] 00h 2f2 - rdpos_y[10:8] rdpos_x[11:8] 00h 2f3 rdvalue_r - 2f4 rdvalue_g - 2f5 rdvalue_b - 2f8 delta_e n rgb_or dr avrg_e n avrg_p ol col_od d col_even 00h 2f9 delta_t ype - dmmy_e n dmmy_p os 8 0h
TW8833/TW8833s C tft display controll er intersil|techwell 44 rev a 10/25 /2010 fosd index (hex) 7 6 5 4 3 2 1 0 reset value 300 - miren font_s witch osd_swi tch 00h 301 - status - 302 - dbgwin dbg 06h 303 osd de delay 06 h 304 blink italic uline bsen auto clear fr_rac_ sel 0 0h 305 - fbitext rd_sel - i2cosdr ad 00h 306 i2cosdrad 00h 307 fdata 00h 308 fattribute 00h 309 i2cfontrad 00h 30a i2cfontdat 00h 30b madd 31h 30c - osdon table_wsel 00h 30d table_con_h 00h 30e table_con_l 00h 310 win1en win1mc olor win1cve xt - xw in1zoom ywin1zoom 00 h 311 win1asel win1alpha 00h 312 - win1hstr - win1vstr 00h 313 win1hstr 00h 314 win1vstr 00h 315 - win1height 00h 316 - win1width 00h 317 - win1reg sta win1bc 00h 318 win1bce n - win1bcwid 00h 319 - win1hbwid 00h 31a - win1vbwid 00h 31b win1ben win1ten win1eff win1bse l win1sc 00h 31c win1sce n win1chs pc win1cvs pc win1scwid 00h 31d win1chspc win1cvspc 00h 31e win1bgc win1bsc 00h 31f win1regsta 00h 320 win2en win2mc olor win2cve xt xwin2zoom ywin2zoom 00h 321 win2asel win2alph a 00h 322 - win2hstr - win2vstr 00h 323 win2hstr 00h 324 win2vstr 00h
TW8833/TW8833s C tft display controll er intersil|techwell 45 rev a 10/25 /2010 325 - win2height 00h 326 - win2width 00h 327 - win2reg sta win2bc 00h 328 win2bce n - win2bcwid 00h 329 - win2hbwid 00h 32a - win2vbwid 00h 32b win2ben win2ten win2eff win2bse l w in2sc 00h 32c win2sce n win2chs pc win2cvs pc win2scwid 00h 32d win2chspc win2cvspc 00h 32e win2bgc win2bsc 00h 32f win2regsta 00h 330 win3en win3mc olor win3cve xt - xwin3zoom ywin3zoom 00h 331 win3asel win3alpha 00h 332 - win3hstr - win3vstr 00h 333 w in3hstr 00h 334 win3vstr 00h 335 - win3height 00h 336 - win3width 00h 337 - win3reg sta win3bc 00h 338 win3bce n - win3bcwid 00h 339 - win3hbwid 00h 33a - win3vbwid 00h 33b win3ben win3ten win3eff win3bse l win3sc 00h 33c win3sce n win3chs pc win3cvs pc win3scwid 00h 33d win3chspc win3cvspc 00h 33e win3bgc win3bsc 00h 33f win3regsta 00h 340 win4en win4mc olor win4cve xt - xwin4zoom ywin4zoom 00h 341 win4asel win4alpha 00h 342 - win4hstr - win4vstr 00h 343 win4hstr 00h 344 win4vstr 00h 345 - win4he ight 00h 346 - win4width 00h 347 - win4reg sta win4bc 00h 348 win4bce n - win4bcwid 00h 349 - win4hbwid 00h 34a - win4vbwid 00h
TW8833/TW8833s C tft display controll er intersil|techwell 46 rev a 10/25 /2010 34b win4ben win4ten win4eff win4bse l win4sc 00h 34c win4sce n win4chs pc win4cvs pc win4scwid 00h 34d win4chspc win4cvspc 00h 34e win4bgc win4bsc 00h 34f win4regsta 00h spi osd (for TW8833s only) index (hex) 7 6 5 4 3 2 1 0 reset value 400 bltsel - mixodr osdrst 00h 40f timadj 45 h 410 lutwe lutinc_sel - lut_byt 00 h 411 lutaddr 00 h 412 lutdata 00 h 420 win0lpe win0_pe rpi x win0_al pha_ena - win0_en a 00h 421 - win0_hs_hb 00h 422 win0_hs_lb 00 h 423 - win0_vs_hb 00h 424 win0_vs_lb 00h 425 - win0_hl_hb 00h 426 win0_hl_lb 00h 427 - win0_vl_hb 00h 428 win0_vl_lb 00h 429 bfm0_ast_hb 00 h 42a bfm0_ast_mb 00 h 42b bfm0_ast_ lb 00 h 42c - bfm0_hl_hb 00 h 42d bfm0_hl_lb 00h 42e - bfm0_v l_hb 00 h 42f bfm0_v l_lb 00h 430 - wfm0_hs_hb 00h 431 wfm0_hs_lb 00h 43 2 - wfm0_vs_hb 00h 433 wfm0_vs_lb 00h 434 - win0_alpha 00 h 435 win0_lphnum 00h 436 win0_lpvnum 00h 437 win0_fd 00h 440 win1lpe win1_pe rpix win1_al pha_ena - win1_en a 00h 441 - win1_hs_hb 00h 442 win1_hs_lb 00h 443 - win1_vs_hb 00h 444 win1_vs_lb 00h
TW8833/TW8833s C tft display controll er intersil|techwell 47 rev a 10/25 /2010 445 - win1_hl_hb 00 h 446 win1_hl_lb 00h 447 - win1_vl_hb 00 h 448 win1_vl_lb 00h 449 bfm1_ast_hb 00h 44a bfm1_as t_mb 00 h 44b bfm1_ast_lb 00 h 44c - bfm1_hl_hb 00 h 44d bfm1_hl_lb 00h 44e - bfm1_v l_hb 00 h 44f bf m1_v l_lb 00h 450 - wfm1_hs_hb 00 h 451 wfm1_hs_lb 00h 452 - wfm1_vs_hb 00 h 453 wfm1_vs_lb 00h 454 - win1_alpha 00 h 455 win1_lphnum 00h 456 win1_lpvnu m 00h 457 win1_fd 00h
TW8833/TW8833s C tft display controll er intersil|techwell 48 rev a 10/25 /2010 spi interface index (hex) 7 6 5 4 3 2 1 0 reset value 480 - host spi_mode - osd spi_mode 00h 481 - edge_s el cycle_e n - dma_no nv 00h 483 dma_sel dma_reg_mode wr_cnt_num 40h 484 - busy_c heck wr_mod e dma_st r 00h 485 dma_wait spi _wait 80h 486 dma_reg_page 04h 487 index 90h 488 dma_length[15:8] 00h 489 dma_length[7:0] 00h 48a wr_reg1_rg 00h 48b wr_reg2_rg 00h 48c wr_reg3_rg 00h 48d wr_reg4_rg 00h 48e wr_reg5_rg 00h 490 buf1 00h 491 buf2 00h 492 buf3 00h 493 buf4 00h 4 94 buf5 00h 495 buf6 00h 496 buf7 00h 497 buf8 00h 498 status_cmd_rg 05h 499 - busy_p ol busy_bit 08h 49a dma_length[23:16] 00h
TW8833/TW8833s C tft display controll er intersil|techwell 49 rev a 10/25 /2010 register description 0x000 C product id code register (id) bit function r/w description reset 7 - 3 id r TW8833 product id code 06 2 - 0 revision r revision number 0 0x002 C irq bit function r/w description reset 7 int7 r/w reserved - 6 int6 r/w reserved - 5 int5 r/w vertical display end interrupt. 1 4 int4 r/w spi - dma completion interrupt. reset when written. 0 3 int3 r/w end of font osd display interrupt. reset when written 0 2 int2 r/w end of spi - dma window interrup t 0 1 int1 r/w video detection interrupt. the detection corresponds to the input selection. 0 0 int0 r/w video loss interrupt. the source selectio n corresponds to the ipsel register. 1 0x003 C imask bit function r/w description reset 7 - 0 imask r/w interrupt mask for irq status register. an 1 for any bit masks the interrupt for that specific bit. ff 0x006 C srst bit function r/w description re set 7 srst w chip soft reset by writing 1 to this bit. no register will be a ffected by this action. it is a self - resetting bit. 0 6 reserved r/w reserved - 5 ainc r/w 2 - wire host interface auto index increment control 1 = disable 0 = enable 0 4 tck div r/w tcclk divider control 1 = ? 0 = 1 0 3 trud l r/w t rudl pin control. . 1 = high 0 = low 0 2 tclr l r/w tc lrl pin control . 1 = high 0 = low 0 1 trsp r/w tr sp output direction . 1 = trspt 0 = tr spb 0 0 tcsp r/w tcsp output direction. 1 = tcspl 0 = tcspr 0
TW8833/TW8833s C tft display controll er intersil|techwell 50 rev a 10/25 /2010 0x007 C output ctrl i bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 tconsel r/w tcon pin output mode control 0 = tcon 1 = serial rgb 2 = n/a 3 = y - adc data 4 = c - adc d ata 5 = v - adc data 6 = test 7 = n/a 0 0x00 8 C output ctrl i i bit function r/w description reset 7 - 6 tckdrv r/w tcclk drive strength 0 = disable 1 = 4 ma 2 = 8 ma 3 = 12ma 0 5 reserved r/w reserved - 4 tri_en r/w 1 = tristate all output pins 1 3 - 0 gpos el r/w gpo pin output control 0 = negtive irq controlled by irq and imask registers 1 = positive irq controlled by irq and imask registers 2 = decoder vdloss 3 = n/a 4 = n/a 5 = vact2 6 = tcpolp 7 = field 8 = decoder field rate (hz50) 9 = sde (serial rgb d e) a = pwm2 output b = 0 c = 1 , it needs to set 0x0302[5 - 4] = 0 and 0x302[3 - 0] = f. d,e,f = n/a 0
TW8833/TW8833s C tft display controll er intersil|techwell 51 rev a 10/25 /2010 0x009 C gpo control bit function r/w description reset 7 gpoen2 r/w spi cs, spi - d1, spi - d0, spi clk output control 1 = enable gpo function 0 = no rmal spi function 0 6 reserved r/w reserved - 5 gpo 5 r/w gpo 5 (spics) output control when enabled 0 4 - 3 reserved r/w reserved - 2 gpo2 r/w gpo2 (spi - d1) output control when enabled 0 1 gpo1 r/w gpo1 (spi - d0) output control when enabled 0 0 gpo0 r/w g po0 (spiclk) output control when enabled 0 0x01f C test bit function r/w description reset 7 - 0 test r/w 4 = dtest1 6 = dactest1 7 = dactest2 9 = cctest b = clamp test 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 52 rev a 10/25 /2010 0x0db C fpwm_hi bit function r/w description reset 7 reserved r/w reserved - 6 - 4 fpclk _dela y r/w clock delay selection of fpclk 000 = normal clock path select 001 = 1 ns delay clock path select 010 = 2 ns delay clock path select 011 = 3 ns delay clock path select 100 = normal clock path select with polarity inversion 101 = 1 ns del ay clock path select with polarity inversion 110 = 2 ns delay clock path select with polarity inversion 111 = 3 ns delay clock path select with polarity inversion 0 3 - 2 fpwm2[9 - 8] r/w pwm2 frequency control msb. a 10 - bit register. 1 1 - 0 fpwm1[9 - 8] r/w pw m1 frequency control msb. a 10 - bit register. 1 0x0dc C fpwm1_lo bit function r/w description reset 7 - 0 fpwm1 [7 - 0] r/w pwm1 frequency control lsb. a 10 - bit register. freq = 27mhz / 256 / fpwm1 8 0 0x0 dd C dpwm1 bit function r/w description reset 7 - 0 dp wm1 r/w pwm1 duty cycle control. duty = ( dpwm1 / 256 ) % 0 0x0de C fpwm2_lo bit function r/w description reset 7 - 0 fpwm2[7 - 0] r/w pwm2 frequency control lsb. a 10 - bit register. freq = 27mhz / 256 / fpwm2 80 0x0df C dpwm2 bit function r/w description reset 7 - 0 dpwm2 r/w pwm2 duty cycle control. duty = ( dpwm2 / 256 ) % 8 0
TW8833/TW8833s C tft display controll er intersil|techwell 5 3 rev a 10/25 /2010 0x0e0 C ledc control i bit function r/w description reset 7 led_ oven r/w over voltage feedback control 0 = disable 1 = enable 1 6 led_ oien r/w over current feedback control 0 = disable 1 = enable 1 5 led_ uien r/w protection control 0 = disable 1 = enable 1 4 led_ fben r/w ledc feedback loop control 0 = open loop 1 = close loop 1 3 - 2 reserved r/w reserved - 1 led a _ pd r/w ledc analog block power down. 0 = analog block power up. 1 = analog block power down . 1 0 ledc _ en r/w ledc digital block enable control 0 = ledc digital block disable. 1 = ledc digital block enable. 0 0x0e1 C ledc sense control bit function r/w description reset 7 - 4 vfb r/w lamp voltage threshold from 0.25v to 2.05v in 0.12v per step. 0 0 = 0.25v ff = 2.05v 0 3 - 0 vop r/w over voltage threshold control. factory use only. a 0x0e2 C ledc control ii bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 4 ledc _st r ledc status - 3 - 0 lstp r/w ledc feedback gain control with 1h being the smallest gain. 4
TW8833/TW8833s C tft display controll er intersil|techwell 54 rev a 10/25 /2010 0x0e3 C ledc pwm bit function r/w description reset 7 - 0 ledc_ fpwm r/w ledc pwm control frequency fpwm[6:0] : led pwm (13.5mhz / fpwm) 4 0 0x0e4 C ledc dim frequency bit function r/w descript ion reset 7 - 0 ledc_ fdim r/w ledc dimming frequency control. 13.18khz / fdim 84 0x0e5 C ledc dim control bit function r/w description reset 7 dmode r/w 0 = ledc digital output disable 1 = ledc digital output enable 0 6 - 0 ledc_ ddim r/w led dimming contr ol 0 = full brightness 7f = lowest brightness 0 0 0x0e6 C ledc pwmtop bit function r/w description reset 7 - 0 pwmtop r/w factory use only 20
TW8833/TW8833s C tft display controll er intersil|techwell 55 rev a 10/25 /2010 0x0e8 C dcdc control i bit function r/w description reset 7 dc_ oven r/w over voltage feedback con trol 0 = disable 1 = enable 1 6 dc_ oien r/w over current feedback control 0 = disable 1 = enable 1 5 dc_ uien r/w under current feedback control 0 = disable 1 = enable 1 4 dc_ fben r/w led feedback loop control 0 = open loop 1 = close loop 1 3 - 2 reserved r/w reserved 0 1 dca _ pd r/w dc sense block power down. 0 = sense block power up. 1 = sense block power down. 1 0 dc _ en r/w dc digital block enable control 0 = dc converter digital block disable. 1 = dc converter digital block enable. 0 0x0e9 C dcdc se nse control bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 2 dc_ fb r/w fb sense threshold control 0 =1.48v 1 = 1.38v 2 = 1. 28v 3 = 1.18v 2 1 - 0 vop r/w reserved 2 0x0ea C dcdc control ii bit function r/ w description reset 7 - 6 reserved r/w reserved - 5 - 4 dc _st r dcdc status - 3 - 0 dc_ lstp r/w dcdc feedback gain control with 1h being the smallest gain. 4
TW8833/TW8833s C tft display controll er intersil|techwell 56 rev a 10/25 /2010 0x0eb C dcdc pwm bit function r/w description reset 7 - 0 dc_ fpwm r/w dcdc pwm control frequency fpwm[7 :0] : led pwm (13.5mhz / fpwm) 4 0 0x0ec C dcdc pwmtop bit function r/w description reset 7 - 0 dc_ pwmtop r/w factory use only 20 0x0ed C vcom - dc offset control bit function r/w description reset 7 - 0 vc - offset r/w vcom dc output offset control fr om 0.67v to 2.64v 80 0x0ee C vcom - ac amp control bit function r/w description reset 7 reserved r/w reserved - 6 vcom_iref r/w vcom iref control. factory use only. 1 5 - 0 vcom_amp r/w vcom - ac amplitude control from 0 to 3.3v 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 57 rev a 10/25 /2010 0x0f0 C dac i bit func tion r/w description reset 7 dac_pd r/w 1 = dac power down 1 6 - 4 dac_vcm r/w output common mode selection 4 3 - 0 dac _ gain r/w dac channel gain 8 0x0f1 C dac ii bit function r/w description reset 7 - 4 reserved r/w reserved - 3 dac_ckinv r/w dac clock polarity control 0 2 dac_ckdly r/w dac clock delay control 0 1 dactog r/w dac output toggle control. 1 = toggling 0 = no toggling 1 0 dacinv r/w dac output inversion 1 = inversion 0 = normal 0 0x0f6 C clock_div bit function r/w description reset 7 - 4 spiclk_div r/w these bits control the spi clock divider as follow. 0 = 1 1 = ? 2 = 1/3 3 = 1/4 0 3 - 0 pclk_div r/w these bits control the pclk divider as follow 0 = 1 1 = ? 2 = 1/3 3 = ? 4 = 1/8 0 0x0f7 C sspll bit function r/w description reset 7 re served r/w reserved - 6 edge_sel_p r/w edge selection for sspll . factory use only 0 5 - 4 sspll_cp_x 4 r/w sspll_x4 cp selection . factory use only. 1ua / 5ua / 10ua / 15ua 1 3 - 2 sspll_lp_x4 r/w sspll_x4 lp selection among 80k to 20k . factory use only. 1 1 - 0 sspll_lp_x8 r/w sspll_x8 lp selection among 18k to 0.8k . factory use only. 2 0x0f8 C sspll control registers bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 fpll[19 - 16] r/w part of a 20 - bit register that control the pll center fre quency as below. pll oscillation frequency = 108mhz * f pll / 2 ^ 17 / 2^ post 1
TW8833/TW8833s C tft display controll er intersil|techwell 58 rev a 10/25 /2010 0x0f9 C sspll frequency control registers bit function r/w description reset 7 - 0 fpll[15 - 8] r/w part of a 20 - bit register that control the pll center frequency as below. pl l oscillation frequency = 108mhz * f pll / 2 ^ 17 / 2^ post 2 0 0x0fa C sspll frequency control registers bit function r/w description reset 7 - 0 fpll[7 - 0] r/w part of a 20 - bit register that control the pll center frequency as below. pll oscillation frequ ency = 108mhz * f pll / 2 ^ 17 / 2^ post 0 0 0x0fb C sspll modulation frequency control registers bit function r/w description reset 7 - 0 fss[7 - 0] r/w s pread spectrum modulation frequency = 27mhz * fss / 2^16 40 0x0fc C sspll bit function r/w descriptio n reset 7 pd_sspll r/w pd_sspll, pll power down control 1 = power down 0 6 - 4 ssd r/w spread spectrum gain divider. see ssg description. 3 3 - 0 ssg r/w spread spectrum gain control. the frequency deviation is controller by a center spreading saw tooth waveform. the controlling frequency is determined by fss and its associated equation. the percentage of peak - to - peak spread or deviation of the center frequency is determined by the following equation. devpp = ssg * 2^8 / (fpll * 2^ssd) * 100 % 0
TW8833/TW8833s C tft display controll er intersil|techwell 59 rev a 10/25 /2010 0x0fd C sspll analog control registers bit function r/w description reset 7 - 6 post r/w post, pll post divider 0 = 1 1 = 1/2 2 = 1/4 3 = 1 /8 set pll post divider larger than 1 is recommended 0 5 - 4 vco r/w vco range control. 0 = 13.5 ~ 27mhz 2 = 54 ~ 108mhz 1 = 27 ~ 54 mhz 3 = 108 ~ 216 mhz 1 3 reserved r/w reserved - 2 - 0 ipmp r/w charge pump currents (ua) 0 = 1.5 1 = 2.5 2 = 5 3 = 10 4 = 20 5 = 40 6 = 80 7 = 160 1 0x0fe C fpga debug bit function r/w description reset 7 - 0 shue r/w fpga debug use only fpga dac output selection 00
TW8833/TW8833s C tft display controll er intersil|techwell 60 rev a 10/25 /2010 decoder 0x101 C chip status register (cstatus) bit functi on r/w description reset 7 vdloss r 1 = video not present. (sync is not detected in number of consecutive line periods specified by misscnt register) 0 = video detected. - 6 hlock r 1 = horizontal sync pll is locked to the incoming video source. 0 = hor izontal sync pll is not locked. - 5 slock r 1 = sub - carrier pll is locked to the incoming video source. 0 = sub - carrier pll is not locked. - 4 field r 0 = odd field is being decoded. 1 = even field is being decoded. - 3 vlock r 1 = vertical logic is loc ked to the incoming video source. 0 = vertical logic is not locked. - 2 reserved r reserved - 1 mono r 1 = no color burst signal detected. 0 = color burst signal detected. - 0 det50 r 0 = 60hz source detected 1 = 50hz source detected the actual vertical scanning frequency depends on the current standard invoked. - 0x102 C input format (inform) bit function r/w description reset 7 reserved r/w reserved - 6 fc27 r/w 1 = input crystal clock frequency is 27mhz. 0 = square pixel mode. must use 24.54mhz fo r 60hz field rate source or 29.5mhz for 50hz field rate source. 1 5 - 4 ifsel r/w 0 = composite video decoding 1 = s - video decoding 2 = component video decoding (interlace input) 3 = component video decoding (progressive input) 0 3 - 2 ysel r/w these two bit s control the input video selection. it selects the composite video source or luma source. 0 = yin0 1 = yin1 2 = yin2 3 = n/a 0 1 c sel r/w this bit select the c channel input 0 = c vin0 1 = n/a 0 0 vsel r/w this bit select the v channel input 0 = vin0 1 = n/a 0
TW8833/TW8833s C tft display controll er intersil|techwell 61 rev a 10/25 /2010 0x103 C reserved bit function r/w description reset 7 - 0 reserved r/w reserved - 0x104 C hsync delay control bit function r/w description reset 7 reserved r/w reserved - 6 - 5 ckhy r/w color killer time constan t 0 = fastest 3 = slowest 0 4 - 0 reserved r/w reserved - 0x105 C anti - aliasing bit function r/w description reset 7 - 6 reserved r/w reserved - 5 save r/w 0 = normal adc current. 1 = enable adc current saving mode. 0 4 reserved r/w reserved - 3 fbpy r/w 0 = disable 1 = enable y channel anti - aliasing filter (decoder mode) 0 2 fbpc r/w 0 = disable 1 = enable c channel anti - aliasing filter (decoder mode) 0 1 fbpv r/w 0 = disable 1 = enable v channel anti - aliasing filter (decoder m ode) 0 0 dec_sel r/w afe control selection 0 = disable 1 = decoder input mode 0
TW8833/TW8833s C tft display controll er intersil|techwell 62 rev a 10/25 /2010 0x106 C analog control register (acntl) bit function r/w description reset 7 sreset w a 1 written to this bit resets the device to its default state but all register cont ent remain unchanged. this bit is self - resetting. 0 6 iref r/w 0 = internal current reference 1. 1 = internal current reference 2. 0 5 vref r/w 0 = internal voltage reference. 1 = internal voltage reference shut down. 0 4 agc_en r/w 0 = agc loop functi on enabled. 1 = agc loop function disabled. gain is set to by agcgain. 0 3 clk_pdn r/w 0 = normal clock operation. 1 = 27 mhz clock in power down mode. 0 2 y_pdn r/w 0 = luma adc in normal operation. 1 = luma adc in power down mode. 0 1 c_pdn r/w 0 = ch roma adc in normal operation. 1 = chroma adc in power down mode. 0 0 v_pdn r/w 0 = v channel adc in normal operation. 1 = v channel adc in power down mode. 0 0x107 C cropping register, high (crop_hi) bit function r/w description reset 7 - 6 vdelay_hi r/w bit[9:8] of the 10 - bit vertical delay register. 0 5 - 4 vactive_hi r/w bit[9:8] of the 10 - bit vactive register. refer to description on reg0x09 for its shadow register. 1 3 - 2 hdelay_hi r/w bit[9:8] of the 10 - bit horizontal delay register. 0 1 - 0 hactive_ hi r/w bit[9:8] of the 10 - bit hactive register. 2 0x108 C vertical delay register, low (vdelay_lo) bit function r/w description reset 7 - 0 vdelay_lo r/w bit[7:0] of the 10 - bit vertical delay register. the two msbs are in the crop_hi register. it defines the number of lines between the leading edge of vsync and the start of the active video. 12
TW8833/TW8833s C tft display controll er intersil|techwell 63 rev a 10/25 /2010 0x109 C vertical active register, low (vactive_lo) bit function r/w description reset 7 - 0 vactive_lo r/w bit[7:0] of the 10 - bit vertical active register. the tw o msbs are in the crop_hi register. it defines the number of active video lines per frame output. the vactive register has a shadow register for use with 50hz source when atreg of reg0x1c is not set. this register can be accessed through the same index a ddress by first changing the format standard to any 50hz standard. 20 0x10a C horizontal delay register, low (hdelay_lo) bit function r/w description reset 7 - 0 hdelay_lo r/w bit[7:0] of the 10 - bit horizontal delay register. the two msbs are in the c rop_hi register. it defines the number of pixels between the leading edge of the hsync and the start of the image cropping for active video. the hdelay_lo register has two shadow registers for use with pal and secam sources respectively. these register c an be accessed using the same index address by first changing the decoding format to the corresponding standard. 0a 0x10b C horizontal active register, low (hactive_lo) bit function r/w description reset 7 - 0 hactive_lo r/w bit[7:0] of the 10 - bit horizon tal active register. the two msbs are in the crop_hi register. it defines the number of active pixels per line output. d0
TW8833/TW8833s C tft display controll er intersil|techwell 64 rev a 10/25 /2010 0x10c C control register i (cntrl1) bit function r/w description reset 7 pbw r/w combined with vtl[3], there are four different chr oma bandwidth can be selected. 1 = wide chroma bpf bw 0 = normal chroma bpf bw 1 6 dem r/w color killer sensitivity 1 = low 0 = high 1 5 palsw r/w 1 = pal switch sensitivity low. 0 = pal switch sensitivity norma l. 0 4 set7 r/w 1 = the black level is 7.5 ire above the blank level. 0 = the black level is the same as the blank level. 0 3 comb r/w 1 = adaptive comb filter on for ntsc/pal 0 = notch filter 1 2 hcomp r/w 1 = operation mode 1. (recommended) 0 = operat ion mode 0. 1 1 ycomb r/w this bit controls the comb operation when there is no color burst. 1 = no comb 0 = comb. 0 0 pdly r/w pal delay line 1 = disable 0 = enable 0 0x10d C cc /wss control bit function r/w description reset 7 - 6 reserved r/w reserved - 5 wssen r/w 0 = disable wss decoding 1 = enable 0 4 - 0 ccoddline r/w these bits control the closed caption decoding line number in case of odd field 00 0x110 C brightness cont rol register (bright) bit function r/w description reset 7 - 0 brightness r/w these bits control the brightness. they have value of C 128 to 127 in 2?s complement form. positive value increases brightness. a value 0 has no effect on the data. 00
TW8833/TW8833s C tft display controll er intersil|techwell 65 rev a 10/25 /2010 0x111 C c ontrast control register (contrast) bit function r/w description reset 7 - 0 contrast r/w these bits control the contrast. they have value of 0 to 3.98 (ffh). a value of 100 (64h) yields a gain of 100%. the gain ranges from 0 to 255% 5c 0x112 C sharpness control register i (sharpness) bit function r/w description reset 7 scurve r/w this bit controls the center frequency of the peaking filter. the corresponding gain adjustment is hflt. 0 = low 1 = center 0 6 vsf r/w this bit is for interna l used. 0 5 - 4 cti r/w color transient improvement level control. there are 4 enhancement levels with 0 being the lowest and 3 being the highest. 1 3 - 0 sharp r/w these bits control the amount of sharpness enhancement on the luminance signals. there are 16 levels of control with ?0? having no effect on the output image and ?15? being the strongest. 1 0x113 C chroma (u) gain register (sat_u) bit function r/w description reset 7 - 0 sat_u r/w these bits control the digital gain adjustment to the u (or cb) co mponent of the digital video signal. the color saturation can be adjusted by adjusting the u and v color gain components by the same amount in the normal situation. the u and v can also be adjusted independently to provide greater flexibility. the range of adjustment is 0 to 200%. 80 0x114 C chroma (v) gain register (sat_v) bit function r/w description reset 7 - 0 sat_v r/w these bits control the digital gain adjustment to the v (or cr) component of the digital video signal. the color saturation can be adj usted by adjusting the u and v color gain components by the same amount in the normal situation. the u and v can also be adjusted independently to provide greater flexibility. the range of adjustment is 0 to 200%. 80
TW8833/TW8833s C tft display controll er intersil|techwell 66 rev a 10/25 /2010 0x115 C hue control register (hue) b it function r/w description reset 7 - 0 hue r/w these bits control the color hue. it is in 2?s complement form with 0 being the center value. positive value results in red hue and negative value gives green hue. 00 0x116 C reserved bit function r/w descri ption reset 7 - 0 reserved r/w reserved - 0x117 C vertical peaking control i bit function r/w description reset 7 - 4 shcor r/w these bits provide coring function for the sharpness control. 8 3 reserved r/w reserved - 2 - 0 vshp r/w vertical peaking gain c ontrol 0 0x118 C coring control register (coring) bit function r/w description reset 7 - 6 ctcor r/w these bits control the coring function for the cti. it has internal step size of 2. 1 5 - 4 ccor r/w these bits control the low level coring function for t he cb/cr output. 0 3 - 2 vcor r/w these bits control the coring function of the vertical peaking logic. it has an internal step size of 2. 1 1 - 0 cif r/w these bits control the if compensation level. 0 = none 1 = 1.5 db 2 = 3 db 3 = 6 db 0 0x119 C reserved bit function r/w description reset 7 - 0 reserved r/w reserved -
TW8833/TW8833s C tft display controll er intersil|techwell 67 rev a 10/25 /2010 0x11a C cc/eds status register (cc_status) bit function r/w description reset 7 ccvlden r/w reserved - 6 eds_en r/w 0 = eds data is not transferred to the cc_data fifo. 1 = eds data is transferred to the cc_data fifo. 0 5 cc_en r/w 0 = cc data is not transferred to the cc_data fifo. 1 = cc data is transferred to the cc_data fifo. 0 4 parity r 0 = data in cc_data has no error. 1 = data in cc_data has odd p arity error. - 3 ff_ovf r 0 = an overflow has not occurred. 1 = an overflow has occurred in the cc_data fifo. - 2 ff_emp r 0 = cc_data fifo is empty. 1 = cc_data fifo has data available. - 1 cc_eds r 0 = closed caption data is in cc_data register. 1 = e xtended data service data is in cc_data register. - 0 lo_hi r 0 = low byte of the 16 - bit word is in the cc_data register. 1 = high byte of the 16 - bit word is in the cc_data register. - 0x11b C cc/eds data register (cc_data) bit function r/w description reset 7 - 0 cc_data r these bits store the incoming closed caption or even field closed caption data. - 0x11c C standard selection (sdt) bit function r/w description reset 7 detstus r 0 = idle 1 = detection in progress - 6 - 4 stdnow r current standard i nvoked 0 = ntsc(m) 1 = pal (b,d,g,h,i) 2 = secam 3 = ntsc4.43 4 = pal (m) 5 = pal (cn) 6 = pal 60 7 = n/a - 3 atreg r/w 1 = disable the shadow registers. 0 = enable vactive and hdelay sha dow registers value depending on standard 0 2 - 0 standard r/w standard selection 0 = ntsc(m) 1 = pal (b,d,g,h,i) 2 = secam 3 = ntsc4.43 4 = pal (m) 5 = pal (cn) 6 = pal 60 7 = auto detecti on 7
TW8833/TW8833s C tft display controll er intersil|techwell 68 rev a 10/25 /2010 0x11d C standard recognition (sdtr) bit function r/w description reset 7 atstart r/w writing 1 to this bit will manually initiate the auto format detection process. this bit is a self - resetting bit. 0 6 pal6_en r/w 1 = enable recognition of pal60 . 0 = disable recognition. 1 5 paln_en r/w 1 = enable recognition of pal (cn). 0 = disable recognition. 1 4 palm_en r/w 1 = enable recognition of pal (m). 0 = disable recognition. 1 3 nt44_en r/w 1 = enable recognition of ntsc 4.43. 0 = disable recognit ion. 1 2 sec_en r/w 1 = enable recognition of secam. 0 = disable recognition. 1 1 palb_en r/w 1 = enable recognition of pal (b,d,g,h,i). 0 = disable recognition. 1 0 ntsc_en r/w 1 = enable recognition of ntsc (m). 0 = disable recognition. 1 0x11e C co mponent video format (cvfmt) bit function r/w description reset 7 reserved r /w reserved - 6 - 4 cvstd r component video input format detection. 0 = 480i 1 = 576i 2 = 480p 3 = 576p others = na - 3 - 0 cvfmt r/w component video format selection. 0 = 480i 1 = 576i 2 = 480p 3 = 576p 8 = auto others = n/a 0 0x11f C test bit function r/w description reset 7 - 0 reserved r/w reserved -
TW8833/TW8833s C tft display controll er intersil|techwell 69 rev a 10/25 /2010 0x120 C clamping gain (clmpg) bit function r/w description reset 7 - 4 clpend r/w these 4 bits set the end time of the clamping pulse in the increment of 8 system clocks. the clamping time is determined by this together with clpst. 5 3 - 0 clpst r/w these 4 bits set the start time of the clamping pulse in the increment of 8 system clocks. it is referenced to pclamp position. 0 0x121 C individual agc gain (iagc) bit function r/w description reset 7 - 4 nmgain r/w these bits control the normal agc loop maximum correction value. 2 3 - 1 wpgain r/w peak agc loop gain control. 1 0 agcgain8 r/w this bit is the msb of the 9 - bit register that controls the agc gain when agc loop is disabled. 0 0x122 C agc gain (agcgain) bit function r/w description reset 7 - 0 agcgain r/w these bits are the lower 8 bits of the 9 - bit register that co ntrols the agc gain when agc loop is disabled. f0 0x123 C white peak threshold (peakwt) bit function r/w description reset 7 - 0 peakwt r/w these bits control the white peak detection threshold. d8 0x124 C clamp level (clmpl) bit function r/w description reset 7 clmpld r/w 0 = clamping level is set by clmpl. 1 = clamping level preset at 60d. 1 6 - 0 clmpl r/w these bits determine the clamping level of the y channel. 3c
TW8833/TW8833s C tft display controll er intersil|techwell 70 rev a 10/25 /2010 0x125 C sync amplitude (synct) bit function r/w description reset 7 synctd r/w 0 = r eference sync amplitude is set by synct. 1 = reference sync amplitude is preset to 38h. 1 6 - 0 synct r/w these bits determine the standard sync pulse amplitude for agc reference. 38 0x126 C sync miss count register (misscnt) bit function r/w description reset 7 - 4 misscnt r/w these bits set the threshold for horizontal sync miss count threshold. 4 3 - 0 hswin r/w these bits set the size for the horizontal sync detection window. 4 0x127 C clamp position register (pclamp) bit function r/w description rese t 7 - 0 pclamp r/w these bits set the clamping position from the pll sync edge 38 0x128 C vertical control i bit function r/w description reset 7 - 6 vlcki r/w vertical lock in time. 0 = fastest 3 = slowest. 0 5 - 4 vlcko r/w vertic al lock out time. 0 = fastest 3 = slowest. 0 3 vmode r/w vertical detection window. 0 = vertical count down mode 1 = search mode 0 2 detv r/w 0 = normal vsync logic 1 = recommended for special application only 0 1 afld r/w auto field generation control 0 = off 1 = on 0 0 vint r/w vertical integration time control. 0 = short 1 = normal 0
TW8833/TW8833s C tft display controll er intersil|techwell 71 rev a 10/25 /2010 0x129 C vertical control ii bit function r/w description reset 7 - 5 bsht r/w burst pll center frequency control. 0 4 - 0 vsht r/w vsync output delay control in the increment of half line length 00 0x12a C color killer level control bit function r/w description reset 7 - 6 ckilmax r/w these bits control the amount of color killer hysteres is. the hysteresis amount is proportional to the value. 1 5 - 0 ckilmin r/w these bits control the color killer threshold. larger value gives lower killer level. 38 0x12b C comb filter control bit function r/w description reset 7 fcomb r/w 1 = non - adap tive comb 0 = adaptive comb. 0 6 - 4 htl r/w adaptive comb filter control (factory use only). 4 3 vtl1 r/w comb filter bandwidth control 0 2 - 0 vtl r/w adaptive comb filter threshold control (factory use only) 4 0x12c C luma delay and hfilter control bit function r/w description reset 7 cklm r/w color killer mode. 0 = normal 1 = fast (for special application) 0 6 - 4 ydly r/w luma delay fine adjustment. this 2?s complement number provides C 4 to +3 unit delay control. 3 3 - 0 hflt r/w peaking control 2. the peaking curve is controlled by scurve bit. 0
TW8833/TW8833s C tft display controll er intersil|techwell 72 rev a 10/25 /2010 0x12d C miscellaneous control register i (misc1) bit function r/w description reset 7 hplc r/w reserved 0 6 evcnt r/w 0 = normal operation 1 = even field counter in special mode 0 5 palc r/w reserved 0 4 sdet r/w id detection sensitivity. 1 is recommended. 1 3 tbc_en r/w 0 = tbc off 1 = internal tbc enabled. (test purpose only) 0 2 bypass r/w it controls the standard detection and shou ld be set to ?1? in normal use. 1 1 syout r/w 0 = hsync is always generated 1 = hsync is disabled when video loss is detected 0 0 hadv r/w reserved 0 0x12e C miscellaneous control register ii (misc2) bit function r/w description reset 7 - 6 hpm r/w hori zontal pll acquisition time. 0 = slow 1 = medium 2 = auto 3 = fast 2 5 - 4 acct r/w acc time constant 0 = no acc 1 = slow 2 = medium 3 = fast 2 3 - 2 spm r/w burst pll control. 0 = slowest 1 = slow 2 = fast 3 = fastest 1 1 - 0 cbw r/w chroma low pass filter bandwidth control. 0 = low 1 = medium 2 = high 3 = na 1
TW8833/TW8833s C tft display controll er intersil|techwell 73 rev a 10/25 /2010 0x12f C miscellaneous control iii (misc3) bit function r/w description reset 7 nkill r/w 1 = ena ble noisy signal color killer function in ntsc mode. 0 = disable 1 6 pkill r/w 1 = enable automatic noisy color killer function in pal mode. 0 = disable 1 5 skill r/w 1 = enable automatic noisy color killer function in secam mode. 0 = disable 1 4 cbal r /w 0 = normal output 1 = special output mode. 0 3 fcs r/w 1 = force decoder output value determined by ccs. 0 = disable 0 2 lcs r/w 1 = enable pre - determined output value indicated by ccs when video loss is detected. 0 = disable 0 1 ccs r/w when fcs is set high or video loss condition is detected when lcs is set high, one of two colors display can be selected. 1 = blue color 0 = black 0 0 bst r/w 1 = enable blue stretch. 0 = disable 0 0x130 C macrovision detection bit function r/w description reset 7 sid_fail r 1 = secam id detection failed - 6 pid_fail r 1 = pal id detection failed - 5 fsc_fail r 1 = fsc frequency detection failed - 4 slock_fail r 1 = sub - carrier lock detection failed - 3 csbad r 1 = macrovision color stripe detection may be un - r eliable - 2 mcvsn r 1 = macrovision agc pulse detected. 0 = not detected. - 1 cstripe r 1 = macrovision color stripe protection burst detected. 0 = not detected. - 0 ctype r this bit is valid only when color stripe protection is detected, i.e. cstripe=1 . 1 = type 2 color stripe protection 0 = type 3 color stripe protection -
TW8833/TW8833s C tft display controll er intersil|techwell 74 rev a 10/25 /2010 0x131 C chip status ii (cstatus2) bit function r/w description reset 7 vcr r vcr signal indicator - 6 wkair r weak signal indicator 2 - 5 wkair1 r weak signal indicator1 - 4 v std r standard line per field indicator - 3 nintl r non - interlaced signal indicator - 2 wssdet r 1 = wss data detected 0 = not detected. - 1 edsdet r 1 = eds data detected 0 = not detected. - 0 ccdet r 1 = cc data detected 0 = not detected. - 0x1 3 2 C h monitor (hfref) bit function r/w description reset 7 - 0 hfref, etc. r horizontal line frequency indicator href[9:2] / gval[8:1] / pherrdo / cgaino / bampo / minavg / sythrd / syamp - 0x133 C clamp mode(clmd) bit function r/w description reset 7 - 6 f rm r/w free run mode. 0 , 1 = auto mode 2 = 60 hz 3 = 50 hz 0 5 - 4 ynr r/w y hf noise reduction. 0 = none 1 = smallest 2 = small 3 = medium 0 3 - 2 clmd r/w clamp ing mode control. 0 = sync top 1 = auto 2 = pedestal 3 = na 1 1 - 0 psp r/w slice level. 0 = low 1 = medium 2 = high 3 = na 1
TW8833/TW8833s C tft display controll er intersil|techwell 75 rev a 10/25 /2010 0x134 C id detection control (nse n/ssen/psen/wkth) bit function r/w description reset 7 - 6 index r/w these two bits indicate which of the four lower 6 - bit registers is currently being controlled. the write sequence is a two steps process unless the same register is written. a write of { id,000000} selects one of the four registers to be written. a subsequent write will actually write into the register. 0 5 - 0 nsen / ssen / psen / wkth r/w idx = 0 controls the ntsc id detection sensitivity (nsen). idx = 1 c ontrols the secam id detection sensitivity (ssen). idx = 2 controls the pal id detection sensitivity (psen). idx = 3 controls the weak signal detection sensitivity (wkth). 1a/ 20 / 1c / 2a 0x135 C clamp control (clcntl) bit function r/w description reset 7 ctest r/w clamping control for debug use. 0 6 yclen r/w 0 = enable y channel clamp 1 = disable 0 5 cclen r/w 0 = enable c channel clamp 1 = disable 0 4 vclen r/w 0 = enable v channel clamp 1 = disable 0 3 gtest r/w 0 = normal operation 1 = test 0 2 vlpf r/w sync filter bandwidth control 0 1 ckly r/w clamping current control 1. 0 0 cklc r/w clamping current control 2. 0 0x140 C wss 0 bit function r/w description reset 7 - 6 r eserved r/w reserved - 5 - 0 wss0 r these are the sliced wss data bit 19 to 14 - 0x141 C wss1 bit function r/w description reset 7 crcerr r this is the crc error indicator for 525 - line wss 0 = no crc error 1 = crc error - 6 wssfld r these bit i ndicates the detected wss field information 0 = odd 1 = even - 5 - 0 wss1 r these bits represent the sliced wss data bit 13 to 8. - 0x142 C wss2 bit function r/w description reset 7 - 0 wss2 r these bits represent the sliced wss bi t 7 to 0. -
TW8833/TW8833s C tft display controll er intersil|techwell 76 rev a 10/25 /2010 scaler 0x201 C general scaler control bit function r/w description reset 7 mirror r/w 1 = enable horizontal mirror output 0 = normal output 0 6 pwen r/w 1 = enable panoramic / water glass display 0 = normal display 0 5 pxdbl r/w 1 = enable pixel doubling function. 0 = disabled 0 4 lndbl r/w 1 = enable line doubling function 0 = disabled 0 3 lnext r/w reserved for factory use. 0 2 lnfix r/w 1 = fix the scaler output line number defined by register lntt. 0 = output line number determined b y scaling factor. 0 1 valock r/w 1 = output active start position tracks the input active position 0 = output active start position defined by va_pos register. 0 0 smode r/w scaler mode selection 1 = scaling from the start of the field / frame 0 = scalin g from the start of the input active 0 0x202 C scaling offset control bit function r/w description reset 7 - 6 rdly r/w scaling buffer read out delay in lines 0 5 - 0 foffset r/w scaling initial offset control 20 0x203 C xscale_lo bit function r/w descript ion reset 7 - 0 xscale_lo r/w up scaling ratio control in x - direction. a 16 - bit register. the scaling ratio is defined as 2000h / xscale. 0 0 0x204 C xscale_hi bit function r/w description reset 7 - 0 xscale_hi r/w up scaling ratio control in x - direction. a 16 - bit register. the scaling ratio is defined as 2000h / xscale 20
TW8833/TW8833s C tft display controll er intersil|techwell 77 rev a 10/25 /2010 0x205 C yscale_lo bit function r/w description reset 7 - 0 yscale_lo r/w up / down scaling ratio control in y - direction. a 16 - bit register. the scaling ratio is defined as 2000h / yscale . 0 0 0x206 C yscale_hi bit function r/w description reset 7 - 0 yscale_hi r/w up / down scaling ratio control in y - direction. a 16 - bit register. the scaling ratio is defined as 2000h / yscale 20 0x207 C pxscale bit function r/w description reset 7 - 0 pxsc ale r/w initial scaling value for the panoramic / water glass display in increment of 4. msb 8 - bit of a 12 - bit register. 80 0x208 C pxinc bit function r/w description reset 7 - 0 pxinc [7 - 0] r/w increment step value for the panoramic / water glass display. the step is in 2?s complement format for both positive and negative increment. 10 0x209 C hdscale_lo bit function r/w description reset 7 - 0 hdscale_lo r/w down scaling control in x - direction. a 12 - bit register. the down scaling ratio is defined as 100h / hdscale 00 0x20a C hdscale_hi bit function r/w description reset 7 reserved r/w reserved - 6 vanom r/w va control. factory use only. 0 5 ceven r/w reserved 0 4 hft r/w down scaler filter control. 1 = on 0 = off 0 3 - 0 hdscale_hi r/w down scaling co ntrol in x - direction. a 12 - bit register. the down scaling ratio is defined as 100h / hdscale 1
TW8833/TW8833s C tft display controll er intersil|techwell 78 rev a 10/25 /2010 0x20b C hdelay2 bit function r/w description reset 7 - 0 hdelay2 r/w scaler buffer data output delay in number of pixels in relation to the h sync. 30 0x20c C hactive2_lo bit function r/w description reset 7 - 0 hactive2 r/w scaler data output length in number of pixels. a 10 - bit register. d0 0x20d C hactive2_hi bit function r/w description reset 7 - 6 hactive2_hi r/w scaler data output length in number of pixels . a 10 - bit register 2 5 ckosel r/w pixel clock output selection. 0 = divided clock specified by ckdiv 1 = un - divided clock 0 4 ckp r/w pixel clock polarity control. 0 = active high 1= active low 0 3 vsp r/w fpvs outp ut polarity control. 0 = active high 1= active low 0 2 hsp r/w fphs output polarity control. 0 = active high 1= active low 0 1 - 0 ckdiv r/w pixel clock output frequency division control. 0 = 1 1 = ? 2 = 1/3 3 = ? 0 0x20e C hpadj_hi bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 4 lntt_hi r/w it controls the scaler total output lines when lnfix=1. it is used in special case. a 10 - bit register. 0 3 - 0 hpadj_hi r/w blanking h period adjustment. a 12 - bit 2?s complement register. 0 0x20f C hpadj_lo bit function r/w description reset 7 - 0 hpadj_lo r/w blanking h period adjustment. a 12 - bit 2?s complement register 00 0x210 C ha_pos bit function r/w descrip tion reset 7 - 0 ha_pos r/w output de position control relative to the internal reference in number of output clock 10
TW8833/TW8833s C tft display controll er intersil|techwell 79 rev a 10/25 /2010 0x211 C ha_len_lo bit function r/w description reset 7 - 0 halen_lo r/w output de length control in number of the output clocks. a 12 - bit register 0 0 0x212 C ha_len_hi bit function r/w description reset 7 - 4 pxscale r/w initial x scaling factor. lsb 4 - bit of a 12 - bit register. 0 3 - 0 halen_hi r/w output de length control in number of the output clocks. a 12 - bit register 3 0x213 C hs_pos b it function r/w description reset 7 - 0 hs_pos r/w output h sync position relative to internal reference in number of output clocks. 10 0x214 C hs_len bit function r/w description reset 7 - 4 pxinc[11 - 8] r/w msb 4 - bit of a 12 - bit register that defines the s caling increment for both panorama and waterglass display. it works with pxscale. 2 3 - 0 hs_len r/w output h sync length in number of output clocks. 0 0x215 C va_pos bit function r/w description reset 7 - 0 va_pos r/w output de position control relative to the internal reference in number of output lines 2 0 0x216 C va_len_lo bit function r/w description reset 7 - 0 halen_lo r/w output de control in number of the output lines. a 12 - bit register 00 0x217 C va_len_hi bit function r/w description reset 7 - 4 px inc _hi r/w output de control in number of the output lines. a 12 - bit register 0 3 - 0 halen_hi r/w output de control in number of the output lines. a 12 - bit register 3
TW8833/TW8833s C tft display controll er intersil|techwell 80 rev a 10/25 /2010 0x218 C vs_len_pos bit function r/w description reset 7 - 6 vs_len r/w output v sync leng th in number of output lines. 0 5 - 0 vs_pos r/w output v sync position relative to internal reference in number of output lines. 00 0x219 C lntt_lo bit function r/w description reset 7 - 0 lntt_lo r/w it controls the scaler total output lines when lnfix=1. it is used in special case. a 10 - bit register. 00 0x21a C dm_top bit function r/w description reset 7 - 0 dm_top r/w these bits control the number of data masked lines (black lines) from the top of de 00 0x21b C dm_bot bit function r/w description reset 7 - 0 dm_bot r/w these bits control the number of data masked lines from the end of de. 00
TW8833/TW8833s C tft display controll er intersil|techwell 81 rev a 10/25 /2010 tcon 0x240 C csp control bit function r/w description reset 7 - 4 cspwid r/w column start pulse width control in number of output clocks. 1 3 - 0 csppos r/w column sta rt pulse position control relative to the leading edge of the de 0 0x241 C clp position bit function r/w description reset 7 - 0 clppos r/w column latch pulse position control relative to either the trailing edge of de of the start of line reference depend ing on clpref 0 0x242 C clp width bit function r/w description reset 7 - 0 clpwid r/w column latch pulse width control in number of output clocks. 01 0x243 C rck control hi bit function r/w description reset 7 reserved r/w reserved - 6 - 4 rckpos_hi r/w r ck position control relative to the leading edge of de in number of output clocks. a 11 - bit register. 0 3 reserved r/w reserved - 2 - 0 rckwid_hi r/w rck width control in number of output clocks. a 11 - bit register. 0 0x244 C rck position lo bit function r /w description reset 7 - 0 rckpos_lo r/w rck position control relative to the leading edge of de in number of output clocks. a 11 - bit register. 0 0 0x245 C rck width lo bit function r/w description reset 7 - 0 rckwid_lo r/w rck width control in number of out put clocks. a 11 - bit register. 0 1
TW8833/TW8833s C tft display controll er intersil|techwell 82 rev a 10/25 /2010 0x246 C roe control hi bit function r/w description reset 7 - 6 roe_ext r/w row driver enable pulse extension control. 0 5 - 4 roepos_hi r/w roe position control relative to the leading edge of de in number of output cloc ks. a 10 - bit register. 0 3 reserved r/w reserved - 2 - 0 roewid_hi r/w roe width control in number of output clocks. a 11 - bit register. 0 0x247 C roe position lo bit function r/w description reset 7 - 0 roepos_lo r/w roe position control relative to the le ading edge of de in number of output clocks. a 10 - bit register. 0 0 0x248 C roe width lo bit function r/w description reset 7 - 0 roewid_lo r/w roe width control in number of output clocks. a 11 - bit register. 01 0x249 C rsp control bit function r/w descrip tion reset 7 - 6 reserved r/w reserved - 5 - 4 rspwid r/w row start pulse width control in number of output lines. 1 3 reserved r/w reserved - 2 - 0 rsppos _hi r/w row start pulse position control relative to the first output de line . an 11 - bit register in 2? s complement form. 0 0x24a C rsp position control bit function r/w description reset 7 - 0 rsp_pos_lo r/w row start pulse position control relative to the first output de line. an 11 - bit register in 2?s complement format. 00
TW8833/TW8833s C tft display controll er intersil|techwell 83 rev a 10/25 /2010 0x24b C cpl position control bit function r/w description reset 7 reserved r/w reserved - 6 - 4 cplpos_hi r/w polarity pulse change position relative to the reference controlled by cplref in number of output clocks. this is a 11 - bit register. 0 3 - 0 cplext r/w polarity pulse extension in number of lines. this is effective in polarity toggle mode 2 only. 0 0x24c C cpl position control lo bit function r/w description reset 7 - 0 cplpos_lo r/w polarity pulse change position relative to the reference controlled by cplref in number of outpu t clocks. this is a 11 - bit register. 1 0 0x24d C tcon control i bit function r/w description reset 7 - 6 roemod r/w roe output mode control. 0 = always low 1 = always high 2 = toggle 3 = n/a 2 5 cplpol r/w polarity pulse polarity control. 0 = active low 1= active high 0 4 rsppol r/w row start pulse polarity control. 0 = active high 1 = active low 0 3 roepol r/w row output enable pulse polarity control. 0 = act ive high 1 = active low 0 2 rckpol r/w rck output plarity control. 0 = active high 1 = active low 0 1 clppol r/w column driver latch pulse polarity control. 0 = active high 1 = active low 0 0 csppol r/w column driver start pulse polarity control. 0 = active high 1 = active low 0
TW8833/TW8833s C tft display controll er intersil|techwell 84 rev a 10/25 /2010 0x24e C tcon control ii bit function r/w description reset 7 cplref r/w polarity pulse change reference point control. it is to be used with cplpos register. 0 = reference to internal line sync 1 = reference to trailing edge of de 0 6 cplswp r/w positive and negative polarity pulse swap. 0 = no swap 0 5 - 4 cpltgm r/w polarity pulses toggle mode control. 0 = fr ame inversion 1 = no frame inversion 2 = frame inversion in blanking period only 0 3 roede r/w row driver output enable control 0 = output in active line 1 = output in every line 0 2 clpref r/w column driver latch pulse po sition reference control. 0 = leading edge of de 1 = trailing edge of de 0 1 clpde r/w column driver latch pulse control. 0 = only output in active line 1 = output in every line 0 0 cspde r/w column driver start pulse control. 0 = only o utput in active line 1 = output in every line. 0
TW8833/TW8833s C tft display controll er intersil|techwell 85 rev a 10/25 /2010 0x 28 0 C image adjustment register bit function r/w description reset 7 - 6 reserved r /w reserved - 5 - 0 hue r /w hue adjustment . these bits control the color hue. the range is +45 degrees to C 45 degrees in 1.4 degree increments. 0 degrees is the default ( with 20h ) 2 0 0x 281 C image adjustment register bit function r/w description reset 7 - 0 contrast_ r r/w red contrast adjustment 80h+ = higher contrast 80h = neutral 80h - = l ower contrast 8 0 0x 282 C image adjustment register bit function r/w description reset 7 - 0 contrast_ g r/w green contrast adjustment 80h+ = higher contrast 80h = neutral 80h - = lower contrast 8 0 0x 283 C image adjustment r egister bit function r/w description reset 7 - 0 contrast_ b r/w blue contrast adjustment 80h+ = higher contrast 80h = neutral 80h - = lower contrast 8 0 0x 284 C image adjustment register bit function r/w description reset 7 - 0 contrast_ y r/w y contrast adjustment 80h+ = higher contrast 80h = neutral 80h - = lower contrast 8 0 0x 285 C image adjustment register bit function r/w description reset 7 - 0 contrast_ cb r/w cb contrast adjustment 80h+ = hig her contrast 80h = neutral 80h - = lower contrast 8 0
TW8833/TW8833s C tft display controll er intersil|techwell 86 rev a 10/25 /2010 0x 286 C image adjustment register bit function r/w description reset 7 - 0 contrast_ cr r/w cr contrast adjustment 80h+ = higher contrast 80h = neutral 80h - = lower contrast 8 0 0x 287 C image adjustment register bit function r/w description reset 7 - 0 brightness _r r/w red brightness adjustment 80h+ = higher brightness 80h = neutral 80h - = lower brightness 8 0 0x 288 C image adjustment register bit function r/w description reset 7 - 0 brightness _ g r/w green brightness adjustment 80h+ = higher brightness 80h = neutral 80h - = lower brightness 8 0 0x 289 C image adjustment register bit function r/w description reset 7 - 0 brightness _ b r/w blue brightness adjustment 80h+ = higher brightness 80h = neutral 80h - = lower brightness 8 0 0x 28a C image adjustment register bit function r/w description reset 7 - 0 brightness _ y r /w y brightness adjustment 80h+ = higher brightness 80h = neutral 80h - = lower brightness 8 0 0x 28b C image adjustment register bit function r/w description reset 7 - 4 h_sharp_ cor r/ w coring function for sharpness contro l 3 3 - 0 h_sharpne ss r/w sharpness adjustment 0
TW8833/TW8833s C tft display controll er intersil|techwell 87 rev a 10/25 /2010 0x 28c C image adjustment register bit function r/w description reset 7 h_sharp_ freq r/ w sharpness frequency select 0 = low freq 1 = high freq 0 6 - 0 reserved r/ w reserved - 0x 2b0 C image adjustment register bit function r/w description reset 7 - 6 reserved r/ w reserved - 5 pedlvl r/w black level selection. 0 = 0 1 = 16d 0 4 whtlvl r/w white level selection. 0 = 235d 1 = 255d 1 3 - 1 reserved r/ w reserved - 0 bw_en r/w 0 = bw stretch disable 1 = bw stretch enable 0 0x 2b1 C image adjustment register bit function r/w description reset 7 - 0 bw_ bslope r/w black side slope. 0 0 = x1 40 = x2 80 = x3 c0h = x4 should not be larger than d0 h 40 0x 2b2 C image adjustment register bit function r/w description reset 7 - 0 bw_ wslope r/w white side slope. 0 0 = x1 40 = x2 80 = x3 c0h = x4 should not be large r than d0 h 40 0x 2b6 C image adjustment register bit function r/w description reset 7 - 0 bw_ black_t ilt r/w tilt point for black stretch 67 0x 2b7 C image adjustment register bit function r/w description reset 7 - 0 bw_ white_t ilt r/w tilt point for white s tretch 94
TW8833/TW8833s C tft display controll er intersil|techwell 88 rev a 10/25 /2010 0x 2bf C test pattern generator register bit function r/w description reset 7 tpg_en r/w 1 = internal test pattern generator enabled 0 = scaler output (default) 0 6 - 4 swap r/w rgb/y c bcr byte swap for color change 0 3 - 0 pat_sel r/w pattern selection. 0: hue map 1: hue map (fine) 2: gray horizontal 17 steps 3: gray vertical 17 steps 4: gray h/v 17x17 steps 5: white rectangle 6: vertical 1 - dot stripe 7: horizontal 1 - dot stripe 8: black/white checker board 9: rgb checker board a: gray horizont al 17 steps + horizontal black stripes b: mitsubishi wqvga test pattern c: flat 100% blue d: ramp e, f: flat 50% gray 0
TW8833/TW8833s C tft display controll er intersil|techwell 89 rev a 10/25 /2010 0x 2e0 C gamma control register bit function r/w description reset 7 gamae_r r/w enable red gamma correction. 0 6 gamae_g r/w ena ble green gamma correction. 0 5 gamae_b r/w enable blue gamma correction. 0 4 reserved r/w reserved - 3 - 2 auto_inc r/w enable gamma table address auto increment for reading/writing gamma data port. 0 = disable 1 = read only 2 = write only 3 = read/write 0 1 - 0 gamma_rg b_indx r/w gamma tables access selection: index address 0x 2e1 to 0x 2e2 are used for gamma table accesses. there are 3 sets of gamma table, one table for one color, sharing the same address port and da ta port. these 2 bits identifies which table is accessed. 0 = rgb gamma table 1 = red gamma table 2 = green gamma table 3 = blue gamma table 0 0x 2e1 C gamma table address port register bit function r/w description reset 7 - 0 gamma_ra m - starting_a ddr r/w gamma table address port. 0 0 0x 2e2 C gamma table data port register bit function r/w description reset 7 - 2 reserved r/w reserved - 1 - 0 gamma_ra m_data[9:8] r/w gamma table data port (upper bits) 0 0x 2e3 C gamma table data port register bit function r/w description reset 7 - 0 gamma_ra m_data[7:0] r/w gamma table data port (lower bits) 0
TW8833/TW8833s C tft display controll er intersil|techwell 90 rev a 10/25 /2010 0x 2e4 C dither option register bit function r/w description reset 7 reserved r/w reserved - 6 - 4 dither_opt io n r/w dither option code "010" is recommended for 6:6:6 output 0 3 reserved r/w reserved - 2 - 0 dither_for mat r/w dither output format selection "001" is recommended for 6:6:6 output 0 dither output selec tion and calculations dither output format selection flat panel rgb bit format output dither option code input lsbs used in dither calculation dither method dither output format selection flat panel rgb bit format output dither option code input lsbs used in dither calculation dither method 000 8:8:8 000 n/a none 100 4:4:4 001 (5) (5) (5) 2x2 010 (5,4) (5,4) (5,4) 2x2 011 (5,4,3) (5,4,3) (5,4,3) 2x2 001 6:6:6 001 (3) (3) (3) 2x2 100 (5,4,3,2) (5,4,3,2) (5,4,3,2) 4x4 010 (3, 2) (3,2)(3,2) 2x2 101 3:3:3 001 (6) (6) (6) 2x2 011 (3,2,1) (3,2,1)(3,2,1) 2x2 010 (6,5) (6,5) (6,5) 2x2 100 (3,2,1,0) (3,2,1,0)(3,2,1,0) 4x4 011 (6,5,4) (6,5,4) (6,5,4) 2x2 010 5:6:5 001 (4) (3) (4) 2x2 100 (6,5,4,3) (6,5,4,3) (6,5,4,3) 4x4 010 (4,3) (3,2) (4,3) 2x2 110 3:3:2 001 (6) (6) (7) 2x2 011 (4,3,2) (3,2) (4,3,2) 2x2 010 (6,5) (6,5) (7,6) 2x2 100 (4,3,2,1) (3,2,1) (4,3,2,1) 4x4 011 (6,5,4) (6,5,4) (6,5,4) 2x2 011 5:5:5 001 (4) (4) (4) 2x2 100 (6,5,4,3) (6,5,4, 3) (7,6,5,4) 4x4 010 (4,3) (4,3) (4,3) 2x2 011 (4,3,2) (4,3,2) (4,3,2) 2x2 100 (4,3,2,1) (4,3,2,1) (4,3,2,1) 4x4
TW8833/TW8833s C tft display controll er intersil|techwell 91 rev a 10/25 /2010 0x 2f0 C rgb level readout register bit function r/w description reset 7 - 0 rdkeypos_ x r/w color level readout posit ion x [7:0] (lsb) 0 0 0x 2f1 C rgb level readout register bit function r/w description reset 7 - 0 rdkeypos_ y r/w color level readout position y [7:0] (lsb) 0 0 0x 2f2 C rgb level readout register bit function r/w description reset 7 reserved r/w reserved - 6 - 4 rdkeypos_ y[10:8] r/w color level readout position y [10:8] (msb) 0 3 - 0 rdkeypos_ x[11:8] r/w color level readout position x [11:8] (msb) 0 0x 2f3 C rgb level readout register bit function r/w description reset 7 - 0 red_lvl r red level - 0x 2f4 C r gb level readout register bit function r/w description reset 7 - 0 grn_lvl r green level - 0x 2f5 C rgb level readout register bit function r/w description reset 7 - 0 blu_lvl r blue level -
TW8833/TW8833s C tft display controll er intersil|techwell 92 rev a 10/25 /2010 0x 2f8 C 8 - bit panel interface register bit function r/w descri ption reset 7 delta_en r/w reserved - 6 rgb_ordr r/w 0 = r - >g - >b order 1 = r - >b - >g order 0 5 avrg_en r/w 1 = averaging on every other line enable 0 = no averaging 0 4 avrg_pol r/w 1 = averaging on even line 0 = averaging on odd line 0 3 - 2 col_odd r/w start color for odd line 0 = r 1 = b 2 = g 3 = n/a 0 1 - 0 col_even r/w start color for even line 0 = r 1 = b 2 = g 3 = n/a 0 0x 2f9 C 8 - bit panel interface register bit function r/w description reset 7 delta_type r/w type selection of 8 - bit interface for averaging 1 = serial rgb 0 = delta rgb 1 6 - 2 reserved r/w reserved - 1 dmmy_en r/w serial rgb mode 1 = s - rgb with dummy 0 = s - rgb without dummy 0 0 dmmy_pos r/w serial rgb dummy byte position 1 = dummy comes first 0 = dummy comes last 0
TW8833/TW8833s C tft display controll er intersil|techwell 93 rev a 10/25 /2010 0x300 C font osd control register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 miren r/w 1 = enable font mirror 0 1 font_switc r/w 1 = bypass font ram fifo 0 0 osd_switch r/w 1 = bypass osd ram fifo 0 0x301 C test register bit function r/w description reset 7 - 1 reserved r/w reserved - 0 status r osd wind ow active status - 0x302 C test register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 4 dbgwin r/w osd debug window selection 0 3 - 0 dbg r/w osd debug signal selection 6 0x303 C font osd control register bit function r/w descript ion reset 7 - 0 osd de delay r/w osd de delay from h - sync 06 0x304 C font osd control register bit function r/w description reset 7 blink r/w 1 = character blinking effect enable 0 6 italic r/w 1 = character italic effect enable. 0 5 uline r/w 1 = c haracter underline effect enable. 0 4 bsen r/w 1 = character bordering/shadowing effect enable. 0 3 - 2 auto r/w osd ram auto increase of write address mode selection. 0 = normal mode 1 = font data or attribute address auto mode 3 = f ont data auto mode(previous attribute data automatic write) 0 1 clear r/w osd ram auto clear mode 0 0 fr_rac_sel r/w font/ osd ram serial bus access 0 = osd ram 1 = font ram access 0
TW8833/TW8833s C tft display controll er intersil|techwell 94 rev a 10/25 /2010 0x305 C font osd control register bit func tion r/w description reset 7 - 6 reserved r /w reserved - 5 fbitext r/w 1 = enable c haracter horizontal extension. 0 4 rd_sel r/w register 0x307 , 308 read mode selection . 0 = normal display 1 = qvga display 0 3 - 1 reserved r/w reserv ed - 0 i2cosdrad r/w osd ram address high 1 - bit (total 9 bits). 0 0x306 C osd ram address register bit function r/w description reset 7 - 0 i2cosdrad r/w osd ram address low 8 - bit (word address for single byte access). 00 0x307 C osd ram data port hi r egister bit function r/w description reset 7 - 0 fdata r/w osd ram data port hi (font data). 00 0x308 C osd ram data port lo register bit function r/w description reset 7 - 0 fattribute r/w osd ram data port lo ( font attribute). 00 0x309 C font ram addre ss register bit function r/w description reset 7 - 0 i2cfontrad r/w serial bus font ram address. 00 0x30a C font ram data port bit function r/w description reset 7 - 0 i2cfontdat r/w serial bus font ram data port. 00 0x30b C multi - color font start posit ion register bit function r/w description reset 7 - 0 madd r/w programmable sram address start position for multi - color fonts . 31
TW8833/TW8833s C tft display controll er intersil|techwell 95 rev a 10/25 /2010 0x30c C font osd control register bit function r/w description reset 7 - 5 reserved r/w reserved - 4 osdon r/w osd on/off con trol 0 = osd on 1 = osd off 0 3 - 0 table_wsel r/w character color look up table write address select. 0 0x30d C character color look - up table data port high byte register bit function r/w description reset 7 - 0 table_con_ h r/w charact er color look up table data port high byte. 00 0x30e C character color look - up table data port low byte register bit function r/w description reset 7 - 0 table_con_ l r/w character color look up table data port low byte. 00 0x310 C osd window1 control r egister bit function r/w description reset 7 win1en r/w osd window #n enable 0 6 win1mcolo r r/w 1 = osd window #n multicolor font enable. 0 5 win1cvext r/w 1 = character vertical extension enable. 0 4 reserved r/w reserved - 3 - 2 xwin1zoom r/w osd wind ow #n horizontal zoom. 0 = no zoom 1 = x2 3 = x3 4 = x4 0 1 - 0 ywin1zoom r/w osd window #n vertical zoom. 0 = no zoom 1 = x2 3 = x3 4 = x4 0 0x311 C osd window1 control register bit function r/w description reset 7 - 4 win1asel r/w window alpha blending color selection. 0 3 - 0 win1alpha r/w osd window #n alpha blending amount. 0
TW8833/TW8833s C tft display controll er intersil|techwell 96 rev a 10/25 /2010 0x312 C osd window1 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 4 win1hstr r/w osd window #n h - start location high 3 bits (total 11 bits). 0 3 - 2 reserved r/w reserved - 1 - 0 win1vstr r/w osd window #n v - start location high 2 bits (total 10 bits). 0 0x313 C osd window1 control register bit function r/w descripti on reset 7 - 0 win1hstr r/w osd window #n h - start location low 8 - bit (1 pixels per step). 00 0x314 C osd window1 control register bit function r/w description reset 7 - 0 win1vstr r/w osd window #n v - start location low 8 - bit (1 scan lines per step). 00 0 x315 C osd window1 control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 0 win1height r/w osd window #n v - height (1 character height per step). 00 0x316 C osd window1 control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 0 win1width r/w osd window #n h - width (1 character width per step). 00 0x317 C osd window1 control register bit function r/w description reset 7 - 5 reserved r/w reserved - 4 win1regsta r/w osd display ram starting address hig h 1 - bit (total 9 bits) of osd window #n. 0 3 - 0 win1bc r/w osd window #n border color control . 0
TW8833/TW8833s C tft display controll er intersil|techwell 97 rev a 10/25 /2010 0x318 C osd window1 control register bit function r/w description reset 7 win1bcen r/w osd window #n border color enable. 0 6 - 5 reserved r/w reserved - 4 - 0 win1bcwid r/w osd window #n border color width (1 pixel or scan line per step). 00 0x319 C osd window1 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win1hbwid r/w osd window #n h - border width (1 pixel per step). 00 0x31a C osd window1 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win1vbwid r/w osd window #n v - border width (1 scan line per step). 00 0x31b C osd window1 control register bit function r/w description reset 7 win1ben r/w osd window #n 3 - d effect enable. 0 6 win1ten r/w osd window #n 3 - d effect top/bottom toggle. 0 5 win1eff r/w osd window #n 3 - d effect level control. 0 4 win1bsel r/w character border/shadow selection. 1 = shadow 0 = bord er 0 3 - 0 win1sc r/w osd window #n shadow color control . 0 0x31c C osd window1 control register bit function r/w description reset 7 win1scen r/w osd window #n shadow enable. 0 6 win1chspc r/w character h - space inside window #n (1 pixel per step) msb b it . 0 5 win1cvspc r/w character v - space inside window #n (1 scan line per step) msb bit . 0 4 - 0 win1scwid r/w osd window #n shadow width. 0
TW8833/TW8833s C tft display controll er intersil|techwell 98 rev a 10/25 /2010 0x31d C osd window1 control register bit function r/w description reset 7 - 4 win1chspc r/w character h - space in side window #n (1 pixel per step) 0 3 - 0 win1cvspc r/w character v - space inside window #n (1 scan line per step). 0 0x31e C osd window1 control register bit function r/w description reset 7 - 4 win1bgc r/w osd window #n background color control 0 3 - 0 w in1bsc r/w osd window #n character border/shadow color control 0 0x31f C osd window1 control register bit function r/w description reset 7 - 0 win1regsta r/w osd display ram starting address low 8 - bit of osd window #n. 00 0x320 C osd window2 control reg ister bit function r/w description reset 7 win2en r/w osd window #n enable 0 6 win2mcolo r r/w 1 = osd window #n multicolor font enable. 0 5 win2cvext r/w 1 = character vertical extension enable. 0 4 reserved r/w reserved - 3 - 2 xwin2zoom r/w osd window #n horizontal zoom 0 = no zoom 1 = x2 3 = x3 4 = x4 0 1 - 0 ywin2zoom r/w osd window #n vertical zoom 0 = no zoom 1 = x2 3 = x3 4 = x4 0 0x321 C osd window2 control register bit function r/w description reset 7 - 4 win2asel r/w window alpha blending color selection. 0 3 - 0 win2alpha r/w osd window #n alpha blending amount. 0
TW8833/TW8833s C tft display controll er intersil|techwell 99 rev a 10/25 /2010 0x322 C osd window2 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 4 win2hstr r/w osd window #n h - start location high 3 bits (total 11 bits). 0 3 - 2 reserved r/w reserved - 1 - 0 win2vstr r/w osd window #n v - start location high 2 bits (total 10 bits). 0 0x323 C osd window2 control register bit function r/w description reset 7 - 0 win2hstr r/w osd window #n h - start location low 8 - bit (1 pixels per step). 00 0x324 C osd window2 control register bit function r/w description reset 7 - 0 win2vstr r/w osd window #n v - start location low 8 - bit (1 scan lines per step). 00 0x32 5 C osd window2 control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 0 win2height r/w osd window #n v - height (1 character height per step). 00 0x326 C osd window2 control register bit function r/w description reset 7 - 6 res erved r/w reserved - 5 - 0 win2width r/w osd window #n h - width (1 character width per step). 00 0x327 C osd window2 control register bit function r/w description reset 7 - 5 reserved r/w reserved - 4 win2regsta r/w osd display ram starting address high 1 - bit (total 9 bits) of osd window #n. 0 3 - 0 win2bc r/w osd window #n border color control . 0
TW8833/TW8833s C tft display controll er intersil|techwell 100 rev a 10/25 /2010 0x328 C osd window2 control register bit function r/w description reset 7 win2bcen r/w osd window #n border color enable. 0 6 - 5 reserved r/w reserved - 4 - 0 win2bcwid r/w osd window #n border color width (1 pixel or scan line per step). 00 0x329 C osd window2 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win2hbwid r/w osd window #n h - border width (1 pixel per step). 00 0x32a C osd window2 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win2vbwid r/w osd window #n v - border width (1 scan line per step). 00 0x32b C osd window2 control register bit function r/w description reset 7 wi n2ben r/w osd window #n 3 - d effect enable. 0 6 win2ten r/w osd window #n 3 - d effect top/bottom toggle. 0 5 win2eff r/w osd window #n 3 - d effect level control. 0 4 win2bsel r/w character border/shadow selection. 1 = shadow 0 = border 0 3 - 0 win2sc r/w osd window #n shadow color control . 0 0x32c C osd window2 control register bit function r/w description reset 7 win2scen r/w osd window #n shadow enable. 0 6 win2chspc r/w character h - space inside window #n (1 pixel per step) msb bit . 0 5 win2cvspc r/w character v - space inside window #n (1 scan line per step) msb bit . 0 4 - 0 win2scwid r/w osd window #n shadow width. 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 101 rev a 10/25 /2010 0x32d C osd window2 control register bit function r/w description reset 7 - 4 win2chspc r/w character h - space inside window #n (1 pixel per step) 0 3 - 0 win2cvspc r/w character v - space inside window #n (1 scan line per step). 0 0x32e C osd window2 control register bit function r/w description reset 7 - 4 win2bgc r/w osd window #n background color contr ol 0 3 - 0 win2bsc r/w osd window #n character border/shadow color control 0 0x32f C osd window2 control register bit function r/w description reset 7 - 0 win2regsta r/w osd display ram starting address low 8 - bit of osd window #n. 0 0 0x330 C osd window3 control register bit function r/w description reset 7 win3en r/w osd window #n enable 0 6 win3mcolo r r/w 1 = osd window #n multicolor font enable. 0 5 win3cvext r/w 1 = character vertical extension enable. 0 4 reserved r/w reserved. - 3 - 2 xwin3zoom r /w osd window #n horizontal zoom 0 = no zoom 1 = x2 3 = x3 4 = x4 0 1 - 0 ywin3zoom r/w osd window #n vertical zoom 0 = no zoom 1 = x2 3 = x3 4 = x4 0 0x331 C osd window3 control re gister bit function r/w description reset 7 - 4 win3asel r/w window alpha blending color selection. 0 3 - 0 win3alpha r/w osd window #n alpha blending amount. 0
TW8833/TW8833s C tft display controll er intersil|techwell 102 rev a 10/25 /2010 0x332 C osd window3 control register bit function r/w description reset 7 reserved r/w res erved - 6 - 4 win3hstr r/w osd window #n h - start location high 3 bits (total 11 bits). 0 3 - 2 reserved r/w reserved - 1 - 0 win3vstr r/w osd window #n v - start location high 2 bits (total 10 bits). 0 0x333 C osd window3 control register bit function r/w de scription reset 7 - 0 win3hstr r/w osd window #n h - start location low 8 - bit (1 pixels per step). 00 0x334 C osd window3 control register bit function r/w description reset 7 - 0 win3vstr r/w osd window #n v - start location low 8 - bit (1 scan lines per step) . 00 0x335 C osd window3 control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 0 win3height r/w osd window #n v - height (1 character height per step). 00 0x336 C osd window3 control register bit function r/w description res et 7 - 6 reserved r/w reserved. - 5 - 0 win3width r/w osd window #n h - width (1 character width per step). 00 0x337 C osd window3 control register bit function r/w description reset 7 - 5 reserved r/w reserved. - 4 win3regsta r/w osd display ram starting ad dress high 1 - bit (total 9 bits) of osd window #n. 0 3 - 0 win3bc r/w osd window #n border color control . 0
TW8833/TW8833s C tft display controll er intersil|techwell 103 rev a 10/25 /2010 0x338 C osd window3 control register bit function r/w description reset 7 win3bcen r/w osd window #n border color enable. 0 6 - 5 reserved r/w res erved - 4 - 0 win3bcwid r/w osd window #n border color width (1 pixel or scan line per step). 0 0x339 C osd window3 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win3hbwid r/w osd window #n h - border width (1 pixel per step). 00 0x33a C osd window3 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win3vbwid r/w osd window #n v - border width (1 scan line per step). 00 0x33b C osd window3 control register bit function r/w description r eset 7 win3ben r/w osd window #n 3 - d effect enable. 0 6 win3ten r/w osd window #n 3 - d effect top/bottom toggle. 0 5 win3eff r/w osd window #n 3 - d effect level control. 0 4 win3bsel r/w character border/shadow selection. 1 = shadow 0 = border 0 3 - 0 win3sc r/w osd window #n shadow color control . 0 0x33c C osd window3 control register bit function r/w description reset 7 win3scen r/w osd window #n shadow enable. 0 6 win3chspc r/w character h - space inside window #n (1 pixel per step) msb bit . 0 5 win3cvspc r/w character v - space inside window #n (1 scan line per step) msb bit . 0 4 - 0 win3scwid r/w osd window #n shadow width. 0
TW8833/TW8833s C tft display controll er intersil|techwell 104 rev a 10/25 /2010 0x33d C osd window3 control register bit function r/w description reset 7 - 4 win3chspc r/w character h - sp ace inside window #n (1 pixel per step) 0 3 - 0 win3cvspc r/w character v - space inside window #n (1 scan line per step). 0 0x33e C osd window3 control register bit function r/w description reset 7 - 4 win3bgc r/w osd window #n background color control 0 3 - 0 win3bsc r/w osd window #n character border/shadow color control 0 0x33f C osd window3 control register bit function r/w description reset 7 - 0 win3regsta r/w osd display ram starting address low 8 - bit of osd window #n. 0 0 0x340 C osd window4 co ntrol register bit function r/w description reset 7 win4en r/w osd window #n enable 0 6 win4mcolo r r/w 1 = osd window #n multicolor font enable. 0 5 win4cvext r/w 1 = character vertical extension enable. 0 4 reserved r/w reserved - 3 - 2 xwin4zoom r/w o sd window #n horizontal zoom. 0 = no zoom 1 = x2 3 = x3 4 = x4 0 1 - 0 ywin4zoom r/w osd window #n vertical zoom. 0 = no zoom 1 = x2 3 = x3 4 = x4 0 0x341 C osd window4 control register bit function r/w description reset 7 - 4 win4asel r/w window alpha blending color selection. 0 3 - 0 win4alpha r/w osd window #n alpha blending amount. 0
TW8833/TW8833s C tft display controll er intersil|techwell 105 rev a 10/25 /2010 0x342 C osd window4 control register bit function r/w description reset 7 reserved r/w re served - 6 - 4 win4hstr r/w osd window #n h - start location high 3 bits (total 11 bits). 0 3 - 2 reserved r/w reserved - 1 - 0 win4vstr r/w osd window #n v - start location high 2 bits (total 10 bits). 0 0x343 C osd window4 control register bit function r/w d escription reset 7 - 0 win4hstr r/w osd window #n h - start location low 8 - bit (1 pixels per step). 00 0x344 C osd window4 control register bit function r/w description reset 7 - 0 win4vstr r/w osd window #n v - start location low 8 - bit (1 scan lines per step ). 00 0x345 C osd window4 control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 0 win4height r/w osd window #n v - height (1 character height per step). 00 0x346 C osd window4 control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 - 0 win4width r/w osd window #n h - width (1 character width per step). 00 0x347 C osd window4 control register bit function r/w description reset 7 - 5 reserved r/w reserved - 4 win4regsta r/w osd display ram starting a ddress high 1 - bit (total 9 bits) of osd window #n. 0 3 - 0 win4bc r/w osd window #n border color control . 0
TW8833/TW8833s C tft display controll er intersil|techwell 106 rev a 10/25 /2010 0x348 C osd window4 control register bit function r/w description reset 7 win4bcen r/w osd window #n border color enable. 0 6 - 5 reserved r/w r eserved - 4 - 0 win4bcwid r/w osd window #n border color width (1 pixel or scan line per step). 00 0x349 C osd window4 control register bit function r/w description reset 7 reserved r/w reserved. - 6 - 0 win4hbwid r/w osd window #n h - border width (1 pix el per step). 00 0x34a C osd window4 control register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win4vbwid r/w osd window #n v - border width (1 scan line per step). 00 0x34b C osd window4 control register bit function r/w descr iption reset 7 win4ben r/w osd window #n 3 - d effect enable. 0 6 win4ten r/w osd window #n 3 - d effect top/bottom toggle. 0 5 win4eff r/w osd window #n 3 - d effect level control. 0 4 win4bsel r/w character border/shadow selection. 1 = shadow 0 = border 0 3 - 0 win4sc r/w osd window #n shadow color control . 0 0x34c C osd window4 control register bit function r/w description reset 7 win4scen r/w osd window #n shadow enable. 0 6 win4chspc r/w character h - space inside window #n (1 pixel per step) msb bit . 0 5 win4cvspc r/w character v - space inside window #n (1 scan line per step) msb bit . 0 4 - 0 win4scwid r/w osd window #n shadow width. 0
TW8833/TW8833s C tft display controll er intersil|techwell 107 rev a 10/25 /2010 0x34d C osd window4 control register bit function r/w description reset 7 - 4 win4chspc r/w character h - space inside window #n (1 pixel per step) 0 3 - 0 win4cvspc r/w character v - space inside window #n (1 scan line per step). 0 0x34e C osd window4 control register bit function r/w description reset 7 - 4 win4bgc r/w osd window #n background color control 0 3 - 0 win4bsc r/w osd window #n character border/shadow color control 0 0x34f C osd window4 control register bit function r/w description reset 7 - 0 win4regsta r/w osd display ram starting address low 8 - bit of osd window #n. 0
TW8833/TW8833s C tft display controll er intersil|techwell 108 rev a 10/25 /2010 spi osd 0x400~ 0x457 (for TW8833s only) 0x400 C osd control register bit function r/w description reset 7 - 6 bltsel r/ w blink timer interval selection 0 = 33 frames 1 = 16 frames 2 = 8 frames 3 = 4 frames 0 5 - 2 reserved r/ w reserved. - 1 mixodr r/ w osd and video mixing order 0 = video & spiosd first, then mixed with font osd 1 = video & font osd first, then mixed with spiosd 0 0 osdsrst r/ w soft reset for spiosd section 0 0x40f C spiosd timing adjustment register bit function r/w description reset 7 - 0 timadj r/ w adjust spiosd data read timing 45 0x410 C 8 - bit spiosd look up table access control register bit function r/w description reset 7 lutwe r/w this bit enable look up table write access for mcu or dma 1 = enable look up table write access 0 6 - 5 lutinc_sel r/w lut pointer increment selection: 0 = no increment 1 = byte pointer increments by 1 after each lut data port write ; when it reaches 11, the byte pointer wraps around and the address pointer increments by 1 2 = address pointer increments by 1 after each lut data port write; when it reaches ff, the address pointer wraps around and the byte pointer increments by 1 note: for dma write access, there are only two valid selection, 01 or 10. 0 4 - 2 reserved r/w reserved - 1 - 0 lutbyt r/w byte pointer for the lut access. read reflects the current byte pointer value. if dma is used to read from spi flash and write to lut, the initial byte pointer is specified by 0x486[1:0] (with 0x410[6:5] =10), or 0x487[1:0] (w ith 0x 410[6:5] =01). 0 0x411 C 8 bit spiosd look up table address [7:0] register bit function r/w description reset 7 - 0 lutaddr r/w address pointer to one of the 256 entries of the lut. read reflects the current address pointer value. if dma is used to read from spi flash and write to lut, the initial address is specified by 0x487[7:0] (with 0x410[6:5 ]=10), or 0x486[1:0]#0x487[7:2] (with 0x 410[6:5]=01). 00
TW8833/TW8833s C tft display controll er intersil|techwell 109 rev a 10/25 /2010 0x412 C 8 bit spiosd look up table data port [7:0] register bit function r/w description r eset 7 - 0 lutdata r/w write data to the look up table pointed by the address and byte pointers read returns the data pointed by the address and byte pointers. two reads are required to get the correct data. read does not advance either the address pointe r or byte pointer. this register is not used for dma write lut. 00 0x420 C spiosd window 0 enable register bit function r/w description reset 7 - 6 win0lpe r/w enable window 0 loop back 0 = no looping; displays one time of the loop and then disappears 1 = no looping; displays one time of the loop and then stays at the last frame 2,3 = enable looping 0 5 win0_perpi x r/w osd window 0 alpha blending selection 0 = global window 0 alpha 1 = per pixel alpha 0 4 win0_alpha _ena r/ w osd window 0 alpha blending enable 0 3 - 1 reserved r/w reserved - 0 win0_ena r/w osd window 0 = enable 0 0x421 ~ 0x422 C spiosd window 0 horizontal start [10:0] registers 0x421 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 win0_hs_hb r/w osd window 0 horizontal start (offset from the lcd display first left pixel) high byte 0 0x422 C low byte register bit function r/w description reset 7 - 0 win0_hs_lb r/w osd window 0 horizontal start (offset from the lcd display first left pixel) low byte 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 110 rev a 10/25 /2010 0x423~0x424 C spiosd window 0 vertical start [10:0] registers 0x423 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 win0_vs_hb r/w osd window 0 vertical start (offset from the lcd display top first line) high byte 0 0x424 C low byte register bit function r/w description reset 7 - 0 win0_vs_lb r/w osd window 0 vertical start (offset from the lcd display top first line) low byte 0 0 0x425~0x0426 C spiosd win dow 0 horizontal length [11:0] registers 0x0425 C high byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 win0_hl_hb r/w osd window 0 horizontal length high byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x 426 C low byte register bit function r/w description reset 7 - 0 win0_hl_lb r/w osd window 0 horizontal length low byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0 0x427~0x0428 C spiosd window 0 vertical length [11:0] registers 0x427 C hig h byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 win0_vl_hb r/w osd window 0 vertical length high byte (one line per increment, minimum is 1, maximum is 2048) 0 0x428 C low byte register bit function r/w description res et 7 - 0 win0_vl_lb r/w osd window 0 vertical length low byte (one line per increment, minimum is 1, maximum is 2048) 00
TW8833/TW8833s C tft display controll er intersil|techwell 11 1 rev a 10/25 /2010 0x429 C 0x42b spiosd window 0 buffer memory starting address [23:0] register 0x429 C high byte register bit function r/w description reset 7 - 0 bfm0_ast_h b r/w starting address of the buffer memory area allocated for osd window 0; one byte per increment 00 0x42a C mid byte register bit function r/w description reset 7 - 0 bfm0_ast_m b r/w starting address of the buffer memory area alloca ted for osd window 0 00 0x42b C low byte register bit function r/w description reset 7 - 0 bfm0_ast_l b r/w starting address of the buffer memory area allocated for osd window 0 00 0x42c~0x42d C spiosd window 0 buffer horizontal length [11:0] registers 0x 42c C high byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 bfm0_hl_hb r/w define the window 0 buffer horizontal length per frame, one pixel per increment; max length 2048 pixels. there can be more than one frame horizont ally, but the total pixel horizontally is capped at 4095. 0 0x42d C low byte register bit function r/w description reset 7 - 0 bfm0_hl_lb r/w (see description above) 0 0 0x42e~0x42f C spiosd window 0 buffer vertical length [11:0] registers 0x42e C high by te register bit function r/w description reset 7 - 4 reserved r/w reserved. - 3 - 0 bfm0_vl_hb r/w define the window 0 buffer vertical length per frame, one line per increment; max length 2048 lines) 0 0x42f C low byte register bit function r/w description reset 7 - 0 bfm0_vl_lb r/w (see description above) 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 112 rev a 10/25 /2010 0x430~0x431 C spiosd window 0 image horizontal start [10:0] registers 0x430 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 wfm0_hs_h b r/w define the horizon tal offset of the osd window 0 image from the buffer starting location; one pixel per increment 0 0x431 C low byte register bit function r/w description reset 7 - 0 wfm0_hs_lb r/w (see description above) 00 0x43 2 ~0x43 4 CC spiosd window 0 image vertical s tart [10:0] registers 0x43 2 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 wfm0_vs_h b r/w define the vertical offset of the osd window 0 image from the buffer starting location; one line per increment 0 0x433 C l ow byte register bit function r/w description reset 7 - 0 wfm0_vs_lb r/w (see description above) 0 0 0x434 C spiosd window 0 global alpha value [6:0] register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win0_alpha r/w osd window 0 gl obal alpha blending value min: 0x00 max osd window 0 shown after blending max: 0x7f no osd window 0 shown after blending 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 113 rev a 10/25 /2010 0x435~0x437 C spiosd window 0 loop control registers 0x435 C looping horizontal frame number register bit function r/w descr iption reset 7 - 0 win0_lphnu m r/w number of osd frames horizontally in memory for the window 0 loop display the display starts from number 0. upon reaching the number specified by this register, it returns to number 0. 0 = one frame 1 = two frames ff = 256 frames 0 0 0x436 C looping vertical frame number register bit function r/w description reset 7 - 0 win0_lpvnu m r/w number of osd frames vertically in memory for the window 0 loop display the display starts from number 0. upon finishing the last horizon tal frame, the number increments by 1. 0 = one frame 1 = two frames ff = 256 frames 00 0x437 C frame duration register bit function r/w description reset 7 - 0 win0_fd r/w duration time of each frame (in unit of vsync) 0 = infinite 1 = one vsyn c period ff = 255 vsync periods 00 0x440 C spiosd window 1 enable register bit function r/w description reset 7 - 6 win1lpe r/w enable window 1 loop back 0 = no looping; displays one time of the loop and then disappears 1 = no looping ; displays one time of the loop and then stays at the last frame 2,3 = enable looping 0 5 win1_perpi x r/w osd window 1 alpha blending selection 0 = global window 1 alpha 1 = per pixel alpha 0 4 win1_alpha _ena r/w osd wind ow 1 alpha blending enable 0 3 - 1 reserved r/w reserved - 0 win1_ena r/w osd window 1 (8 bit) enable; priority is lower than osd window 0 0
TW8833/TW8833s C tft display controll er intersil|techwell 114 rev a 10/25 /2010 0x441~ 0x442 C spiosd window 1 horizontal start [10:0] registers 0x441 C high byte register bit function r /w description reset 7 - 3 reserved r/w reserved - 2 - 0 win1_hs_hb r/w osd window 1 horizontal start (offset from the lcd display first left pixel) high byte 0 0x442 C low byte register bit function r/w description reset 7 - 0 win1_hs_lb r/w osd window 1 horizontal start (offset from the lcd display first left pixel) low byte 00 0x443~0x444 C spiosd window 1 vertical start [10:0] registers 0x443 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 win1_vs_hb r/w osd window 1 vertical start (offset from the lcd display top first line) high byte 0 0x444 C low byte register bit function r/w description reset 7 - 0 win1_vs_lb r/w osd window 1 vertical start (offset from the lcd display top first line) low byte 00 0 x445~0x446 C spiosd window 1 horizontal length [11:0] registers 0x445 C high byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 win1_hl_hb r/w osd window 1 horizontal length high byte (one pixel per increment, minimum is 1, maximum is 2048) 0 0x446 C low byte register bit function r/w description reset 7 - 0 win1_hl_lb r/w osd window 1 horizontal length low byte (one pixel per increment, minimum is 1, maximum is 2048) 00
TW8833/TW8833s C tft display controll er intersil|techwell 115 rev a 10/25 /2010 0x447~0x448 C spiosd window 1 vertical length [11:0] registers 0x447 C high byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 win1_vl_hb r/w osd window 1 vertical length high byte (one line per increment, minimum is 1, maximum is 2048) 0 0x448 C low byte register bit functi on r/w description reset 7 - 0 win1_vl_lb r/w osd window 1 vertical length low byte (one line per increment, minimum is 1, maximum is 2048) 00 0x449~0x044b C spiosd window 1 buffer memory starting address [23:0] registers 0x0449 C high byte register bit f unction r/w description reset 7 - 0 bfm1_ast_h b r/w starting address of the buffer memory area allocated for osd window 1; one byte per increment 00 0x44a C mid byte register bit function r/w description reset 7 - 0 bfm1_ast_m b r/w starting address of the b uffer memory area allocated for osd window 1 00 0x44b C low byte register bit function r/w description reset 7 - 0 bfm1_ast_l b r/w starting address of the buffer memory area allocated for osd window 1 00 0x44c~0x044d C spiosd window 1 buffer horizontal length [11:0] registers 0x44c C high byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 bfm1_hl_hb r/w define the window 1 buffer horizontal length per frame, one pixel per increment; max length 2048 pixels. there can be mo re than one frame horizontally, but the total pixel horizontally is capped at 4095. 0 0x44d C low byte register bit function r/w description reset 7 - 0 bfm1_hl_lb r/w (see description above) 00
TW8833/TW8833s C tft display controll er intersil|techwell 116 rev a 10/25 /2010 0x44e~0x44f C spiosd window 1 buffer vertical length [11:0] registers 0x44e C high byte register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 - 0 bfm1_hl_hb r/w define the window 1 buffer vertical length per frame, one line per increment; max length 2048 lines) 0 0x44f C low byte register bit function r/w description reset 7 - 0 bfm1_hl_lb r/w (see description above) 00 0x450~0x51f C spiosd window 1 image horizontal start [10:0] registers 0x450 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved. - 2 - 0 wfm1_hs_h b r/w define the horizontal offset of the osd window 1 image from the buffer starting location in each frame; one pixel per increment 0 0x451 C low byte register bit function r/w description reset 7 - 0 wfm1_hs_lb r/w (see description above) 00 0x452~0x4 53 C spiosd window 1 image vertical start [10:0] registers 0x452 C high byte register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 - 0 wfm1_vs_h b r/w define the vertical offset of the osd window 1 image from the buffer starting location in each frame; one line per increment 0 0x453 C low byte register bit function r/w description reset 7 - 0 wfm1_vs_lb r/w (see description above) 0 0 0x454 C spiosd window 1 global alpha value [6:0] register bit function r/w description reset 7 reserved r/w reserved - 6 - 0 win1_alpha r/w osd window 1 global alpha blending value min: 0x00 max osd window 1 shown after blending max: 0x7f no osd window 1 shown after blending 00
TW8833/TW8833s C tft display controll er intersil|techwell 117 rev a 10/25 /2010 0x455~0x457 C spiosd window 1 loop control registers 0x455 C looping horiz ontal frame number register bit function r/w description reset 7 - 0 win1_lphnu m r/w number of osd frames horizontally in buffer memory for the window 1 loop display the display starts from number 0. upon reaching the number specified by this register, it returns to number 0. 0 = one frame 1 = two frames ff = 256 frames 00 0x456 C looping vertical frame number register bit function r/w description reset 7 - 0 win1_lpvnu m r/w number of osd frames vertically in buffer memory for the window 1 loop display the display starts from number 0. upon finishing the last horizontal frame, the number increments by 1. 0 = one frame 1 = two frames ff = 256 frames 00 0x457 C frame duration register bit function r/w description reset 7 - 0 win1_fd r/w duration time o f each frame (in unit of vsync 0 = infinite 1 = one vsync period ff = 255 vsync periods 00
TW8833/TW8833s C tft display controll er intersil|techwell 118 rev a 10/25 /2010 spi interface 0x480 C spi flash mode control register bit function r/w description reset 7 reserved r/w reserved - 6 - 4 host spi_mode r/ w spi flash read mode 0 = slow 1 = fast 2 = dual 3 = quad 4 = dual - io 5 = quad - io 6 = double edge quad 7,8 = n/a 0 3 reserved r/w reserved - 2 - 0 osd spi_mode r/w spi flash read mode 0 = slow 1 = fast 2 = dual 3 = quad 4 = dual - io 5 = quad - io 6 = double edge quad 7,8 = n/a 0 0x481 C spi flash mode control register bit function r/w description reset 7 - 6 reserved r/w reserved - 5 edge_sel r/w 0 = negative edge 1 = positive edge 0 4 cycle_en r/w enable one cycle delay mode 0 3 - 1 reserved r/w reserved - 0 dma_nonv r/w start mode 0 = immediately 1 = at vertical blank 0 0x483 C dma control regis ter bit function r/w description reset 7 - 6 dma _sel r/w read/write destination 0 = font ram data 1 = chip register 2 = spiosd lut 3 = n/a 1 5 - 4 dma_reg_m ode r/w read / write access mode 0 = increase 1 = decrease 2 = fix 3 = n/a 0 3 - 0 wr_cnt_nu m r/w command write byte count 0
TW8833/TW8833s C tft display controll er intersil|techwell 119 rev a 10/25 /2010 0x484 C flash busy control register bit function r/w description reset 7 - 3 reserved r/w reserved - 2 busy_chec k r/w busy check 0 = no busy check 1 = busy check after command. wait until busy is cleared 0 1 wr_mode r/w spi dma/cmd mode 0 = read, 1 = write 0 0 dma_str r/w start command execution. self cleared. write ? 1 ? = start write ? 0 ? = s top read ? 1 ? = busy read ? 0 ? = ready 0 0x485 C wait control register bit function r/w description reset 7 - 4 dma_wait r/w dma read wait cycle 8 3 - 0 spi_wait r/w spi read /write wait cycle 0 0x486 C dma page register bit function r/w desc ription reset 7 - 0 dma_reg_p age r/w buffer index page or memory start address high byte 0 4 0x487 C dma index register bit function r/w description reset 7 - 0 index r/w buffer index or memory start address low byte 9 0 0x488 C dma length mid byte registe r bit function r/w description reset 7 - 0 dma_lengt h r/w read/write data count mid byte after command 00 0x489 C dma length low byte register bit function r/w description reset 7 - 0 dma_lengt h r/w read/write data count low byte after command 00
TW8833/TW8833s C tft display controll er intersil|techwell 120 rev a 10/25 /2010 0x48a C dma command buffer register bit function r/w description reset 7 - 0 wr_reg1_r g r/w command buffer 1 00 0x48b C dma command buffer2 register bit function r/w description reset 7 - 0 wr_reg2_r g r/w command buffer 2 00 0x48c C dma command buffer3 register bit function r/w description reset 7 - 0 wr_reg3_r g r/w command buffer 3 00 0x48d C dma command buffer4 register bit function r/w description reset 7 - 0 wr_reg4_r g r/w command buffer 4 00 0x48e C dma command buffer5 register bit function r/w descriptio n reset 7 - 0 wr_reg5_r g r/w command buffer 5 00 0x490 C dma read/write buffer1 register bit function r/w description reset 7 - 0 buf1 r/w default read/write buffer 1 00 0x491 C dma read/write buffer2 register bit function r/w description reset 7 - 0 buf2 r/w default read/write buffer 2 00
TW8833/TW8833s C tft display controll er intersil|techwell 121 rev a 10/25 /2010 0x492 C dma read/write buffer3 register bit function r/w description reset 7 - 0 buf3 r/w default read/write buffer 3 00 0x493 C dma read/write buffer4 register bit function r/w description reset 7 - 0 buf4 r/w defaul t read/write buffer 4 00 0x494 C dma read/write buffer5 register bit function r/w description reset 7 - 0 buf5 r/w default read/write buffer 5 00 0x495 C dma read/write buffer6 register bit function r/w description reset 7 - 0 buf6 r/w default read/write buffer 6 00 0x496 C dma read/write buffer7 register bit function r/w description reset 7 - 0 buf7 r/w default read/write buffer 7 00 0x497 C dma read/write buffer8 register bit function r/w description reset 7 - 0 buf8 r/w default read/write buffer 8 0 0 0x498 C spi flash status command register bit function r/w description reset 7 - 0 status_cm d_rg r/w status command 05
TW8833/TW8833s C tft display controll er intersil|techwell 122 rev a 10/25 /2010 0x499 C spi flash busy control register bit function r/w description reset 7 - 4 reserved r/w reserved - 3 busy_pol r/w busy polari ty 0 = low 1 = high 1 2 - 0 busy_bit r/w busy bit in status command 0 0x49a C dma length high byte register bit function r/w description reset 7 - 0 dma_lengt h r/w read/write data count high byte after command 00
TW8833/TW8833s C tft display controll er intersil|techwell 123 rev a 10/25 /2010 copyright notice this manual is copyrighted by intersil corporation. do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of intersil corporation . trademark acknowledgment silicon image, the silicon image logo, panellink ? is a registered trademarks of silicon image, inc. vesa ? is a registered trademark of the video electronics standards association. all other trademarks are the property of their respective ho lders. disclaimer this document provides technical information for the user. intersil corporation reserves the right to modify the information in this document as necessary. the customer should make sure that they have the most recent data sheet version. intersil corporation holds no responsibility for any errors that may appear in this document. customers should take appropriate action to ensure their use of the products does not infringe upon any patents. intersil corporation respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. life support policy intersil corporation products are not authorized for use as critical components in life support devices or systems. revision history date rev ision note 3/18 /2010 i nitial draft 6/01/2010 - correct i2c address - correct pin#38 description - add power consumption information - updated register 0x008[7:6][3:0], 0x2e4, 0x006[3:0], 0x20d[4:2], 0x2e0[1:0],0x24d[5:0], 0x0e8[4], 0x0db[6:4] 10/25/2010 - add font osd function description - change compa n y l ogo

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